INTEGRATING RECEIVER WITH PRECHARGE CIRCUITRY

• US 20110140741A1
• Filed: 10/04/2010
• Published: 06/16/2011
• Est. Priority Date: 10/19/1999
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Werner, Carl W., Chau, Pak S., Garlepp, Bruno W., Horowitz, Mark A., Garrett, Billy W. JR., Donnelly, Kevin S., Sidiropoulos, Stefanos, Zerbe, Jared L.
• Granted Patent: US 8,199,859 B2
• Time in Patent Office: Days
• US Class Current: 327/57
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 2207/108 Wide data ports
• CPC Class Codes: G11C 27/02 Sample-and-hold arrangements G11C27/04 takes precedence
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/106 Data output latches
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1084 Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1087 Data input latches
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/0282 Provision for current-mode coupling
• CPC Class Codes: H04L 25/0296 Arrangements to ensure DC-balance
• CPC Class Codes: H04L 25/0298 Arrangement for terminating transmission lines
• CPC Class Codes: H04L 25/03006 Arrangements for removing intersymbol interference
• CPC Class Codes: H04L 25/03057 : with a recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/08 : Modifications for reducing interference; Modifications for reducing effects due to line faults ; Receiver end arrangements for detecting or overcoming line faults
• CPC Class Codes: H04L 25/4902 : Pulse width modulation; Pulse position modulation
• CPC Class Codes: H04L 25/4917 : using multilevel codes
• CPC Class Codes: H04L 7/0331 : with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence
• CPC Class Codes: H04L 7/0332 : with an integrator-detector

Abstract

A multiphase receiver to compensate for intersymbol interference in the sampling of an input signal includes a first integrating receiver to integrate and sample data of the input signal on a first phase of a clock and a second integrating receiver to integrate and sample data of the input signal on a second phase of the clock. The multiphase receiver also includes an equalization circuit to adjust integration by the first integrating receiver dependent on a result of integration of data previously received by an integrating receiver distinct from the first integrating receiver, and to adjust integration by the second integrating receiver dependent on a result of integration of data previously received by an integrating receiver distinct from the second integrating receiver.

Claims

1. (canceled)

2. An integrated circuit device, comprising:

a sense amplifier comprising an input to receive a present signal representing a present bit, the sense amplifier to produce a decision regarding a logic level of the present bit;

a circuit to precharge the input of the sense amplifier by applying to the input of the sense amplifier a portion of a previous signal representing a previous bit; and

a latch, coupled to the sense amplifier, to output the logic level.

3. The integrated circuit device of claim 2, further comprising an integrator to generate the present signal by integrating an input signal over a regulated time interval.

4. The integrated circuit device of claim 3, where:

the integrator comprises an output coupled to the input of the sense amplifier; and

the circuit to precharge the input of the sense amplifier is coupled to the output of the integrator to adjust integration by the integrator.

5. The integrated circuit device of claim 4, where the circuit to precharge the input of the sense amplifier is to precharge the output of the integrator prior to the integrator integrating the input signal over the regulated time interval.

6. The integrated circuit device of claim 2, where the circuit to precharge the input of the sense amplifier is to compensate for intersymbol interference dynamically as sequential bits are received by adding or subtracting respective voltages generated for respective previously received bits to respective precharge values for integration of the sequential bits.

7. The integrated circuit device of claim 2, where the circuit to precharge the input of the sense amplifier is further to adjust the present signal to compensate for an offset error associated with the sense amplifier.

8. The integrated circuit device of claim 2, where the circuit to precharge the input of the sense amplifier is further to receive the present signal and adjust a future signal by an amount corresponding to a portion of a charge associated with the present bit, where the future signal represents a bit received after the present bit.

9. The integrated circuit device of claim 8, where the circuit to precharge the input of the sense amplifier comprises a register to store an equalization control value, the equalization control value to determine the amount of adjustment to the future signal.

10. The integrated circuit of claim 9, where the circuit to precharge the input of the sense amplifier further comprises a digital-to-analog converter to convert the equalization control value stored in the register to an analog signal.

11. The integrated circuit of claim 2, where the present signal and the logic level as output by the latch are each differential signals.

12. The integrated circuit device of claim 2, embodied as a multiphase receiver, the multiphase receiver comprising an instance of at least the sense amplifier and the latch for each one of first and second phases of an input signal during a clock cycle, each phase corresponding to a respective bit, where:

the instance of the sense amplifier and the latch for the first phase is to resolve a previous bit;

the circuit to precharge the input of the sense amplifier is to adjust the present signal to compensate for intersymbol interference associated with the previous bit; and

the instance of the sense amplifier and the latch for the second phase is to resolve the present bit.

13. The integrated circuit device of claim 12, embodied as a two-phase receiver, where:

the instance of the sense amplifier and the latch for the first phase is to resolve a future bit; and

the circuit to precharge the input of the sense amplifier is to adjust a future signal representing the future bit to compensate for intersymbol interference with the present bit.

14. The integrated circuit device of claim 13, where the circuit to precharge the input of the sense amplifier comprises circuitry corresponding to each one of the first and second phases, including circuitry to adjust the present signal to compensate for intersymbol interference associated with the previous bit and circuitry to adjust the future signal to compensate for intersymbol interference associated with the present bit.

15. The integrated circuit device of claim 13, where the two-phase receiver further comprises, for each phase, an integrator to generate a respective signal by integrating an input signal over a respective regulated time interval.

16. The integrated circuit device of claim 13, where the circuit to precharge the input of the sense amplifier is further to compensate for an offset error associated with an instance of the sense amplifier.

17. A multiphase receiver integrated circuit device, comprising:

a first receive path, comprising;

a first sense amplifier comprising a first input to receive a first signal representing a first bit, the first sense amplifier to produce a decision regarding a first logic level of the first signal;

first circuitry to precharge the first input of the first sense amplifier by applying to the first input a portion of a previous signal representing a previous bit; and

a first latch to output the first logic level; and

a second receive path, comprising;

a second sense amplifier comprising a second input to receive a second signal representing a second bit, the second sense amplifier to produce a decision regarding a second logic level of the second signal;

second circuitry to precharge the second input of the second sense amplifier by applying to the second input a portion of the first signal; and

a second latch to output the second logic level.

18. The multiphase receiver integrated circuit device of claim 17, further comprising:

a third receive path, comprising;

a third sense amplifier comprising a third input to receive a third signal representing a third bit, the third sense amplifier to produce a decision regarding a third logic level of the third signal;

third circuitry to precharge the third input of the third sense amplifier by applying to the third input a portion of the second signal; and

a third latch to output the third logic level.

19. The multiphase receiver integrated circuit device of claim 17, where:

the second sense amplifier is to produce a decision regarding a logic level of the previous signal, and

the first circuitry is coupled to the second receive path to compensate for intersymbol interference with the previous bit.

20. The multiphase receiver integrated circuit device of claim 17, where each receive path further comprises an integrator to generate a respective signal by integrating an input signal over a respective regulated time interval.

21. The multiphase receiver integrated circuit device of claim 20, where:

the first circuitry is coupled to the integrator of the first receive path to adjust integration by the integrator of the first receive path; and

the second circuitry is coupled to the integrator of the second receive path to adjust integration by the integrator of the second receive path.

22. The multiphase receiver integrated circuit device of claim 21, where:

the first circuitry is to precharge the integrator of the first receive path prior to the integrator of the first receive path integrating the input signal over the respective regulated time interval for the first receive path; and

the second circuitry is to precharge the integrator of the second receive path prior to the integrator of the second receive path integrating the input signal over the respective regulated time interval for the second receive path.

23. The multiphase receiver integrated circuit device of claim 17, where the first circuitry and second circuitry are each to compensate for intersymbol interference dynamically as data bits are received by adding or subtracting a voltage generated for a previously received bit to a precharge value for integration of a bit that is to be processed via the corresponding receive path.

24. The multiphase receiver integrated circuit device of claim 17, where the first circuitry and second circuitry are each further to adjust a respective signal to compensate for offset error associated with a corresponding sense amplifier.

25. The multiphase receiver integrated circuit device of claim 17, further comprising, for each receive path, a register to store a control value, the control value to determine an amount of adjustment to a respective signal to be applied by a corresponding one of the first circuitry and second circuitry.

26. The multiphase receiver integrated circuit device of claim 17, further comprising, for each receive path, a register to store an offset error control value, the offset error control value to determine an amount of adjustment to a respective signal to be applied by a respective one of the first circuitry and second circuitry to compensate for input voltage offset error.

27. The multiphase receiver integrated circuit device of claim 17, further comprising, for each receive path, a register to store an equalization control value, the equalization control value to determine an amount of adjustment to a respective signal to be applied by a respective one of the first circuitry and second circuitry to compensate for intersymbol interference with an immediately prior bit.

28. A receiver integrated circuit device, comprising

a receive path, comprising:

a first sense amplifier comprising a first input to receive a first signal representing a first bit, the first sense amplifier to produce a decision regarding a first logic level of the first signal;

first circuitry to precharge the first input of the first sense amplifier by applying to the first input a portion of a previous signal representing a previous bit; and

a first latch to output the first logic level.

29. The receiver integrated circuit device of claim 28, where the first bit is an odd-phase bit and the previous bit is an even-phase bit,

the receiver integrated circuit device further comprising a second receive path comprising:

a second sense amplifier comprising a second input to receive signals representing even-phase bits, the second sense amplifier to produce decisions regarding logic levels of the signals representing the even-phase bits;

second circuitry to precharge the second input of the second sense amplifier by applying to the second input portions of signals representing respective odd-phase bits; and

a second latch to output the logic levels of the signals representing the even-phase bits;

where the first circuitry is coupled to the second receive path to precharge the first input of the first sense amplifier by applying to the first input of the first sense amplifier portions of signals representing respective even-phase bits.

30. The receiver of claim 29, further comprising a phase-adjustment circuit to adjust per-pin timing associated with the signals.

31. The receiver of claim 29, further comprising a data clock recovery system to generate a clock from the signals.

32. The receiver of claim 29, wherein the first circuitry is to add or subtract the portions of the signals representing the respective even-phase bits.