LEVEL SHIFTER USING SR-FLIP FLOP

• US 20110140750A1
• Filed: 12/10/2009
• Published: 06/16/2011
• Est. Priority Date: 12/10/2009
• Status: Active Grant

• Current Assignee: Advantest Corporation
• Original Assignee: Advantest Corporation
• Inventors: KOJIMA, Shoji
• Granted Patent: US 8,030,965 B2
• Time in Patent Office: Days
• US Class Current: 327/198
• CPC Class Codes: H03K 3/356165 using additional transistors in the feedback circuit

Abstract

A level shifter receives an input signal of either a first lower voltage or a first upper voltage which form a voltage pair, and level-shifts the input signal to output an output signal of either a second lower voltage or a second upper voltage. An SR flip-flop generates an output signal which is switched to the second upper voltage upon receiving a positive edge via its set terminal, and is switched to the second lower voltage upon receiving a positive edge via its reset terminal. An AND gate generates the logical AND of a feedback signal having the inverted logical level of the output signal of the SR flip-flop and the input signal, which is output to the set terminal of the SR flip-flop. A NOR gate generates the logical NOR of the feedback signal and the input signal, which is output to the reset terminal of the SR flip-flop.

Claims

1. A level shifter configured to receive an input signal having a level set to one from among a first lower voltage and a first upper voltage which form a voltage pair, and to level-shift the input signal thus received so as to output an output signal having a level set to one from among a second lower voltage and a second upper voltage which form a voltage pair, the level shifter comprising:

an SR flip-flop configured to generate an output signal which is switched to the second upper voltage upon receiving a positive edge of a signal via a set terminal thereof, and which is switched to the second lower voltage upon receiving a positive edge of a signal via a reset terminal thereof;

a first logical gate configured to generate the logical AND of a feedback signal having the inverted logical level of the output signal of the SR flip-flop and the input signal, and to output the logical AND thus generated to the set terminal of the SR flip-flop; and

a second logical gate configured to generate the logical NOR of the feedback signal and the input signal, and to output the logical NOR thus generated to the reset terminal of the SR flip-flop.

5. A level shifter according to claim 1, further comprising Schmitt buffer configured to receive the inverted output signal of the SR flip-flop, and to generate the feedback signal.

8. A level shifter according to claim 1, further comprising a Schmitt inverter configured to receive the output signal of the SR flip-flop, and to generate the feedback signal.

13. A level shifter according to claim 1, wherein the SR flip-flop comprises:

a first lower terminal to which a first lower voltage is to be applied;

a first upper terminal to which a first upper voltage is to be applied, which forms a pair with the first lower voltage;

a second lower terminal to which a second lower voltage is to be applied;

a second upper terminal to which a second upper voltage is to be applied, which forms a pair with the second lower voltage;

one of a set terminal to which a set signal is to be input and an inverting set terminal to which an inverted set signal is to be input;

one of a reset terminal to which a reset signal is to be input and an inverting reset terminal to which an inverted reset signal is to be input;

a cross-coupled inverter arranged between the second lower terminal and the second upper terminal, and configured including a first inverter and a second inverter cross-coupled such that an output terminal of each inverter is connected to an input terminal of the other inverter;

a set unit configured including a first set transistor and a second set transistor configured as N-channel MOSFETs arranged in series between the first lower terminal and the input terminal of the first inverter, and a third set transistor and a fourth set transistor configured as P-channel MOSFETs arranged in series between the input terminal of the second inverter and the first upper terminal, and configured such that the set signal is input to the gate of the first set transistor, and the signal complementary to the set signal is input to the gate of the fourth set transistor; and

a reset unit configured including a first reset transistor and a second reset transistor configured as N-channel MOSFETs arranged in series between the first lower terminal and the input terminal of the second inverter, and a third reset transistor and a fourth reset transistor configured as P-channel MOSFETs arranged in series between the input terminal of the first inverter and the first upper terminal, and configured such that the reset signal is input to the gate of the first reset transistor, and the signal complementary to the reset signal is input to the gate of the fourth reset transistor, wherein the gate of the second set transistor and the gate of the third reset transistor are connected to the output terminal of the second inverter, and wherein the gate of the third set transistor and the gate of the second reset transistor are connected to the output terminal of the first inverter.

18. A test apparatus comprising:

a first circuit block configured to operate by receiving a first lower voltage and a first upper voltage, which form a voltage pair;

a second circuit block configured to operate by receiving a second lower voltage and a second upper voltage, which form a voltage pair; and

a level shifter according to claim 1, configured to receive a signal output from the first circuit block, and to transmit the signal thus received to the second circuit block.

2. A level shifter configured to receive an input signal having a level set to one from among a first lower voltage and a first upper voltage which form a voltage pair, and to level-shift the input signal thus received so as to output an output signal having a level set to one from among a second lower voltage and a second upper voltage which form a voltage pair, the level shifter comprising:

an SR flip-flop configured to generate an output signal which is switched to the second upper voltage upon receiving a negative edge of a signal via an inverting set terminal thereof, and which is switched to the second lower voltage upon receiving a positive edge of a signal via a reset terminal thereof;

a first logical gate configured to generate the logical NAND of a feedback signal having the inverted logical level of the output signal of the SR flip-flop and the input signal, and to output the logical NAND thus generated to the inverting set terminal of the SR flip-flop; and

a second logical gate configured to generate the logical NOR of the feedback signal and the input signal, and to output the logical NOR thus generated to the reset terminal of the SR flip-flop.

6. A level shifter according to claim 2, further comprising Schmitt buffer configured to receive the inverted output signal of the SR flip-flop, and to generate the feedback signal.

7. A level shifter according to claim 2, further comprising a delay circuit configured to receive the inverted output signal of the SR flip-flop, and to generate the feedback signal.

9. A level shifter according to claim 2, further comprising a Schmitt inverter configured to receive the output signal of the SR flip-flop, and to generate the feedback signal.

14. A level shifter according to claim 2, wherein the SR flip-flop comprises:

a first lower terminal to which a first lower voltage is to be applied;

a first upper terminal to which a first upper voltage is to be applied, which forms a pair with the first lower voltage;

a second lower terminal to which a second lower voltage is to be applied;

a second upper terminal to which a second upper voltage is to be applied, which forms a pair with the second lower voltage;

one of a set terminal to which a set signal is to be input and an inverting set terminal to which an inverted set signal is to be input;

one of a reset terminal to which a reset signal is to be input and an inverting reset terminal to which an inverted reset signal is to be input;

a cross-coupled inverter arranged between the second lower terminal and the second upper terminal, and configured including a first inverter and a second inverter cross-coupled such that an output terminal of each inverter is connected to an input terminal of the other inverter;

a set unit configured including a first set transistor and a second set transistor configured as N-channel MOSFETs arranged in series between the first lower terminal and the input terminal of the first inverter, and a third set transistor and a fourth set transistor configured as P-channel MOSFETs arranged in series between the input terminal of the second inverter and the first upper terminal, and configured such that the set signal is input to the gate of the first set transistor, and the signal complementary to the set signal is input to the gate of the fourth set transistor; and

a reset unit configured including a first reset transistor and a second reset transistor configured as N-channel MOSFETs arranged in series between the first lower terminal and the input terminal of the second inverter, and a third reset transistor and a fourth reset transistor configured as P-channel MOSFETs arranged in series between the input terminal of the first inverter and the first upper terminal, and configured such that the reset signal is input to the gate of the first reset transistor, and the signal complementary to the reset signal is input to the gate of the fourth reset transistor,

wherein the gate of the second set transistor and the gate of the third reset transistor are connected to the output terminal of the second inverter,

and wherein the gate of the third set transistor and the gate of the second reset transistor are connected to the output terminal of the first inverter.

19. A test apparatus comprising:

a first circuit block configured to operate by receiving a first lower voltage and a first upper voltage, which form a voltage pair;

a second circuit block configured to operate by receiving a second lower voltage and a second upper voltage, which form a voltage pair; and

a level shifter according to claim 2, configured to receive a signal output from the first circuit block, and to transmit the signal thus received to the second circuit block.

3. A level shifter configured to receive an input signal having a level set to one from among a first lower voltage and a first upper voltage which form a voltage pair, and to level-shift the input signal thus received so as to output an output signal having a level set to one from among a second lower voltage and a second upper voltage which form a voltage pair, the level shifter comprising:

an SR flip-flop configured to generate an output signal which is switched to the second upper voltage upon receiving a positive edge of a signal via a set terminal thereof, and which is switched to the second lower voltage upon receiving a negative edge of a signal via an inverting reset terminal thereof;

a first logical gate configured to generate the logical AND of a feedback signal having the inverted logical level of the output signal of the SR flip-flop and the input signal, and to output the logical AND thus generated to the set terminal of the SR flip-flop; and

a second logical gate configured to generate the logical OR of the feedback signal and the input signal, and to output the logical OR thus generated to the inverting reset terminal of the SR flip-flop.

4. A level shifter configured to receive an input signal having a level set to one from among a first lower voltage and a first upper voltage which form a voltage pair, and to level-shift the input signal thus received so as to output an output signal having a level set to one from among a second lower voltage and a second upper voltage which form a voltage pair, the level shifter comprising:

an SR flip-flop configured to generate an output signal which is switched to the second upper voltage upon receiving a negative edge of a signal via an inverting set terminal thereof, and which is switched to the second lower voltage upon receiving a negative edge of a signal via an inverting reset terminal thereof;

a first logical gate configured to generate the logical NAND of a feedback signal having the inverted logical level of the output signal of the SR flip-flop and the input signal, and to output the logical NAND thus generated to the inverting set terminal of the SR flip-flop; and

a second logical gate configured to generate the logical OR of the feedback signal and the input signal, and to output the logical OR thus generated to the inverting reset terminal of the SR flip-flop.

10-12. -12. (canceled)

20-22. -22. (canceled)