External storage device and method of manufacturing external storage device

• US 20110141681A1
• Filed: 12/06/2010
• Published: 06/16/2011
• Est. Priority Date: 12/15/2009
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Ogawa, Kenta, Nakashiba, Yasutaka
• Granted Patent: US 8,705,238 B2
• Time in Patent Office: Days
• US Class Current: 361/679.31
• CPC Class Codes: G11C 5/005 Circuit means for protection against loss of information of semiconductor storage devices
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48228 the bond pad being disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 23/49855 for flat-cards, e.g. credit cards cards per se G06K19/00
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 27/0688 : Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 28/10 : Inductors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/15183 : in a single layer of the multilayer substrate
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H05K 1/117 : Pads along the edge of rigid circuit boards, e.g. for pluggable connectors
• CPC Class Codes: H05K 2201/0949 : Pad close to a hole, not surrounding the hole if used for surface mounting H05K1/114
• CPC Class Codes: H05K 2201/09845 : Stepped hole, via, edge, bump or conductor
• CPC Class Codes: H05K 2203/0228 : Cutting, sawing, milling or shearing
• CPC Class Codes: H05K 2203/1316 : Moulded encapsulation of mounted components
• CPC Class Codes: H05K 2203/1572 : Processing both sides of a PCB by the same process; Providing a similar arrangement of components on both sides; Making interlayer connections from two sides
• CPC Class Codes: H05K 3/0052 : Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
• CPC Class Codes: H05K 3/284 : for encapsulating mounted components H05K1/185 takes precedence
• CPC Class Codes: Y10T 29/4902 : Electromagnet, transformer or inductor
• CPC Class Codes: Y10T 29/4913 : Assembling to base an electrical component, e.g., capacitor, etc.

Abstract

A storage element is provided in a semiconductor chip, and an inductor and a driver circuit are provided in another semiconductor chip. An external terminal is a contact type terminal, and at least some external terminals are a power supply terminal and a ground terminal. A sealing resin layer is formed over a first surface of an interconnect substrate and seals the semiconductor chips but does not cover the external terminal. The inductor is formed at a surface of the semiconductor chip not facing the interconnect substrate.

Claims

1. An external storage device comprising:

an interconnect substrate;

at least one semiconductor chip disposed over a first surface of said interconnect substrate;

a storage element provided in at least said one semiconductor chip;

an inductor which is provided in at least said one semiconductor chip and which communicates information stored in said storage element to the outside;

a driver circuit which is provided in at least said one semiconductor chip in order to drive said inductor;

a contact type external terminal provided in said interconnect substrate; and

a sealing resin layer which is formed over said first surface of said interconnect substrate and which seals at least said one semiconductor chip and does not cover said external terminal,

wherein said inductor is formed at a surface of said semiconductor chip not facing said interconnect substrate.

2. The external storage device according to claim 1,

wherein said external terminal is a power supply terminal which supplies electric power to at least said driver circuit.

3. The external storage device according to claim 1,

wherein the diameter of said inductor is equal to or less than 1 mm.

4. The external storage device according to claim 1,

wherein said external storage device is of a card type.

5. The external storage device according to claim 1, further comprising:

a guide section which is an uneven section provided using said sealing resin layer.

6. The external storage device according to claim 5,

wherein the planar shape of said external storage device is approximately rectangular or approximately square, and

said guide section is formed at two opposite side surfaces of said external storage device.

7. The external storage device according to claim 1,

wherein first and second semiconductor chips are provided as at least said one semiconductor chip,

said first semiconductor chip has said inductor and said driver circuit,

said second semiconductor chip has said storage element, and

said first and second semiconductor chips are connected to each other through said interconnect substrate.

8. The external storage device according to claim 7, further comprising:

a supporting member located between said first semiconductor chip and said first surface of said interconnect substrate; and

said first semiconductor chip is disposed with an active surface, which has said inductor and said driver circuit, opposite said first surface.

9. The external storage device according to claim 1,

wherein said sealing resin layer has a recess in a region overlapping said inductor when seen in a plan view.

10. The external storage device according to claim 1,

wherein said storage element is nonvolatile.

11. The external storage device according to claim 1,

wherein said external terminal is provided at said first surface of said interconnect substrate.

12. The external storage device according to claim 1,

wherein said external terminal is formed at a second surface of said interconnect substrate which is an opposite surface to said first surface.

13. The external storage device according to claim 1, further comprising:

a penetrating hole for alignment formed in said interconnect substrate.

14. The external storage device according to claim 13, further comprising:

a first protective insulating layer which covers said first surface of said interconnect substrate;

a second protective insulating layer which covers said second surface of said interconnect substrate that is an opposite surface to said first surface

a first opening which is provided in said first protective insulating layer in order to expose said penetrating hole; and

a second opening which is provided in said second protective insulating layer in order to expose said penetrating hole.

15. The external storage device according to claim 1, further comprising:

a housing including said interconnect substrate and said sealing resin layer inside; and

an opening which is provided in a region of said housing facing said first surface of said interconnect substrate and which overlaps said external terminal and said inductor.

16. A method of manufacturing an external storage device, comprising:

disposing at least one semiconductor chip over a first surface of an interconnect substrate having a contact type external terminal; and

forming a sealing resin layer over said first surface of said interconnect substrate such that at least said one semiconductor chip is sealed and said external terminal is not covered,

wherein a storage element is provided in at least said one semiconductor chip,

an inductor which communicates information stored in said storage element to the outside is provided in at least said one semiconductor chip, and

a driver circuit of said inductor is provided in at least said one semiconductor chip.

17. The method according to claim 16,

wherein a penetrating hole for alignment is provided in said interconnect substrate,

in said step of disposing at least said one semiconductor chip over said first surface of said interconnect substrate, plural sets of at least said one semiconductor chip are disposed over said first surface with said penetrating hole as a reference, and

performing alignment with said penetrating hole as a reference from a side of a second surface of said interconnect substrate, which is an opposite surface to said first surface, and then separating said interconnect substrate into pieces in units of a set of at least said one semiconductor chip from said second surface side is included after said step of forming said sealing resin layer over said interconnect substrate.

18. The method according to claim 17,

wherein said interconnect substrate includes a first protective insulating layer which covers said first surface, a second protective insulating layer which covers said second surface that is an opposite surface to said first surface, a first opening which is provided in said first protective insulating layer in order to expose said penetrating hole, and a second opening which is provided in said second protective insulating layer in order to expose said penetrating hole.