LEAKAGE COMPENSATED REFERENCE VOLTAGE GENERATION SYSTEM
First Claim
1. A semiconductor circuit comprising a reference voltage generator and at least one bitline unit,wherein each of said at least one bitline unit comprises:
- first bitcells connected in a parallel connection between a bitline and electrical ground;
a sense amplifier connected to said bitline; and
a pull-up resistor circuit located between a power supply node and said bitline,wherein said reference voltage generator comprises;
a voltage divider circuit connected to said power supply node and electrical ground and a reference voltage line; and
a leakage current simulation circuit including second bitcells connected in a parallel connection between said reference voltage line and said electrical ground, wherein said leakage current simulation circuit provides a leakage current between said reference voltage line and electrical ground,and wherein said sense amplifier generates an output by comparing a voltage in said reference voltage line and said bitline.
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Accused Products
Abstract
An e-fuse sense circuit employs a single ended sense scheme in which the reference voltage is compensated for leakage. A reference voltage generator includes a pull-up resistor of similar value to the selected bitline pull-up resistor. As the sensing trip point is adjusted by selection of a bitline pull-up resistor, a pair of pull-up and pull-down resistors are adjusted together to adjust the impedance of the reference voltage generator. A leakage-path simulation structure including a parallel connection of bitcells is added to the reference voltage generator. The leakage-path simulation structure imitates the bitcells on a bitline in the array of e-fuses. Leakage current on the bitline offsets the bitline voltage by a certain error voltage. The reference voltage is also offset by a fraction of the error voltage to balance the shifts in the ‘1’ and ‘0’ margin levels in the presence of leakage.
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Citations
20 Claims
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1. A semiconductor circuit comprising a reference voltage generator and at least one bitline unit,
wherein each of said at least one bitline unit comprises: -
first bitcells connected in a parallel connection between a bitline and electrical ground; a sense amplifier connected to said bitline; and a pull-up resistor circuit located between a power supply node and said bitline, wherein said reference voltage generator comprises; a voltage divider circuit connected to said power supply node and electrical ground and a reference voltage line; and a leakage current simulation circuit including second bitcells connected in a parallel connection between said reference voltage line and said electrical ground, wherein said leakage current simulation circuit provides a leakage current between said reference voltage line and electrical ground, and wherein said sense amplifier generates an output by comparing a voltage in said reference voltage line and said bitline. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification