Circuits for Reducing Power Consumption of Memory Components

• US 20110141829A1
• Filed: 12/14/2010
• Published: 06/16/2011
• Est. Priority Date: 12/14/2009
• Status: Abandoned Application

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Ware, Frederick A.
• Application Number:
  US12/968,132
• Publication Number:
  US 20110141829A1
• Time in Patent Office: Days
• US Class Current: 365/189.09
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising

Abstract

An integrated circuit including one or more data links. A respective data link includes a precharge circuit, a voltage generator circuit, and a transmitter circuit. The precharge circuit is configured to precharge a data line to a predefined voltage level between transmission of symbols on the data line. The voltage generator circuit is configured to generate one or more transmit voltage levels, wherein a respective transmit voltage level represents a respective symbol to be transmitted on the data line and provide current from a voltage source to a transmitter circuit to drive the data line to a transmit voltage level representing a symbol to be transmitted, wherein the current drawn from the voltage source is independent of previously transmitted symbols. The transmitter circuit is configured to receive the symbol to be transmitted and drive the data line to the transmit voltage level using the current provided by the voltage generator circuit.

Claims

1. An integrated circuit, comprising:

one or more data links, a respective data link including a transmitter circuit configured to transmit a sequence of symbols onto a respective data line, each symbol being represented by one of a plurality of voltage levels, the respective data link including a precharge circuit configured to precharge the data line to a predefined voltage level between transmission of consecutive symbols in the sequence of symbols, the predefined voltage level being different from any of the plurality of voltage levels used to represent the symbols; and

a voltage generator circuit configured to;

generate one or more of the plurality of voltage levels; and

provide current from a voltage source to the transmitter circuit, the transmitter circuit being configured to transmit a respective symbol by driving the respective data line to a respective voltage level using the current provided by the voltage generator circuit, wherein the current drawn from the voltage source during transmission of the respective symbol is independent of the sequence of symbols.

2. The integrated circuit of claim 1, wherein the voltage source supplies a high reference voltage level and a low reference voltage level, and the voltage generator circuit includes:

a first charge-pump voltage supply circuit coupled between the voltage source and the transmitter circuit, and configured to generate a high transmit voltage level that is the sum of the predefined voltage level, and the difference between the high reference voltage level and the low reference voltage level; and

a second charge-pump voltage supply circuit coupled between the voltage source and the transmitter circuit, and configured to generate a low transmit voltage level that is the sum of the predefined voltage level, and the difference between the low reference voltage level and the high reference voltage level.

3. The integrated circuit of claim 2, wherein each of the first and second charge-pump voltage supply circuits includes at least one capacitor, a plurality of switches, and a control circuit configured to selectively close and open the switches to pump charge from the voltage source to the at least one capacitor.

4. The integrated circuit of claim 2, including a switched series capacitor voltage generator circuit configured to generate one or more reference voltages including the high reference voltage level and the low reference voltage level.

5. The integrated circuit of claim 4, wherein the switched series capacitor voltage generator circuit includes:

two or more capacitors coupled in series to the voltage supply;

a transistor coupled to each capacitor, wherein a respective transistor is configured to transfer charge from one terminal of a respective capacitor to another terminal of the respective capacitor in response to a control signal; and

a control circuit coupled to each capacitor, wherein a respective control circuit is configured to;

compare node voltages of the respective capacitor to node voltages of a resistor voltage divider; and

generate the control signal based on the comparison.

6. The integrated circuit of claim 2, including a port for coupling the integrated circuit to the voltage source, wherein the voltage source is external to the integrated circuit.

7. The integrated circuit of claim 6, wherein the external voltage source is an inductive voltage generator that generates one or more reference voltages including the high reference voltage level and the low reference voltage level.

8. The integrated circuit of claim 1, wherein the voltage generator circuit includes:

a first circuit configured to generate a high transmit voltage level that is a voltage level supplied by the voltage source; and

a second circuit configured to generate a low transmit voltage level that is substantially a ground voltage level.

9. The integrated circuit of claim 1, wherein the transmitter circuit has an impedance that substantially matches an impedance of the data line.

10. The integrated circuit of claim 1, wherein the data line is a single ended data line.

11. The integrated circuit of claim 1, including a plurality of the data links, wherein the plurality of data links share a common reference line carrying a reference voltage and each of the data links is configured to be coupled to a single ended data line.

12. The integrated circuit of claim 11, including a switched series capacitor voltage generator circuit configured to generate a plurality of reference voltages including distinct pairs of high and low reference voltage levels for each of the plurality of the data links, wherein each pair of high and low reference voltage levels has a voltage difference that is substantially fixed and substantially the same as the voltage difference as another one of the pairs of high and low reference voltage levels.

13. The integrated circuit of claim 12, wherein the average of the high and low reference voltage levels of respective pairs of data links is offset by a voltage level that is substantially equal to the voltage difference between the high and low reference voltage levels of a respective data link.

14. The integrated circuit of claim 12, wherein a first data link and a second data link in the plurality of data links share the same pair of high and low reference voltage levels in the plurality of reference voltage levels.

15. The integrated circuit of claim 12, wherein a first data link in the plurality of data links uses a first pair of high and low reference voltage levels in the plurality of reference voltage levels and a second data link in the plurality of data links uses a second pair of high and low reference voltage levels in the plurality of reference voltage levels.

16. The integrated circuit of claim 1, including mode control circuitry which, in a first mode, enables the voltage generator circuit, and in a second mode connects a pair of static power supply voltages to the transmitter circuit, wherein the current drawn from the static power supply voltages is dependent on previously transmitted symbols.

17. The integrated circuit of claim 1, wherein the integrated circuit is selected from the group consisting of:

a memory controller; and

a memory device having an array of memory storage cells.

18. The integrated circuit of claim 1, wherein the one or more data links is selected from the group consisting of:

external data links; and

internal data links.

19. A memory module, comprising:

a substrate;

a plurality of the integrated circuits of claim 1 mounted on the substrate.

20. The memory module of claim 19, wherein the each of the plurality of integrated circuits is configured to operate in a first mode, in which current drawn from a voltage source during data transmission is independent on previously transmitted symbols and in a second mode, in which current drawn from a static power supply voltage source during data transmission is dependent on previously transmitted symbols.

21. The memory module of claim 20,

wherein the first mode is a small voltage swing mode;

and

wherein the second mode is large voltage swing mode.

22. A method, comprising:

at an integrated circuit;

receiving a symbol to be transmitted on a data line;

generating one or more transmit voltage levels, wherein a respective transmit voltage level represents a respective symbol to be transmitted on the data line;

providing current from a voltage source to drive the data line to a transmit voltage level representing a symbol to be transmitted, wherein the current drawn from a voltage source is independent of previously transmitted symbols;

driving the data line to the transmit voltage level using the current; and

precharging the data line to a predefined voltage level between transmission of symbols on the data line.

23. The method of claim 22, wherein the one or more transmit voltage levels are generated using one or more charge-pump voltage supply circuits using one or more reference voltages.

24. The method of claim 23, wherein the one or more reference voltages are generated using a switched series capacitor voltage generator circuit.

25. The method of claim 23, wherein the one or more reference voltages are generated using an inductive voltage generator.

26. A method performed by an integrated circuit device coupled to a voltage source and a plurality of data lines, comprising:

transmitting a first symbol, including driving a respective data line to a first voltage level by drawing first current from the voltage source, the first voltage level representing the first symbol;

after transmitting the first symbol and before transmitting a second symbol, precharging the respective data line to a predefined voltage level that is different from the first voltage level;

transmitting the second symbol that is different in symbol value from the first symbol, including driving the respective data line to a second voltage level by drawing second current from the voltage source, the second voltage level representing the second symbol, the second voltage level being different from the predefined voltage level, the second current being substantially the same as the first current;

after transmitting the second symbol and before transmitting a third symbol, precharging the respective data line to the predefined voltage level; and

transmitting the third symbol having a same symbol value as the second symbol, including driving the respective data line to the second voltage level by drawing third current from the voltage source, the second voltage level representing the third symbol, the second voltage level being different from the predefined voltage level, the third current being substantially the same as the second current.