SERIAL COMMUNICATION MODULE WITH MULTIPLE RECEIVER/TRANSMITTERS

• US 20110142074A1
• Filed: 12/16/2009
• Published: 06/16/2011
• Est. Priority Date: 12/16/2009
• Status: Abandoned Application

• Current Assignee: GE Fanuc Intelligent Platforms Incorporated (Fanuc Corporation)
• Original Assignee: GE Fanuc Intelligent Platforms Incorporated (Fanuc Corporation)
• Inventors: Lueckenbach, William Henry
• Application Number:
  US12/639,614
• Publication Number:
  US 20110142074A1
• Time in Patent Office: Days
• US Class Current: 370/475
• CPC Class Codes: H04L 12/40019 Details regarding a bus master
• CPC Class Codes: H04L 12/403 with centralised control, e.g. polling

Abstract

Implementing serial communications between a master module and at least one slave module in a communications network includes initializing a first receiver/transmitter of the master module to space parity, initializing a second receiver/transmitter of the master module to mark parity, and determining whether a first byte of a message is a command byte or a data byte. If the first byte is a data byte, the first byte is transmitted to the at least one slave module using the first receiver/transmitter. If the first byte is a command byte, the first byte is transmitted to the at least one slave module using the second receiver/transmitter.

Claims

1. A method of implementing serial communications between a master module and at least one slave module in a communications network, said method comprising:

initializing a first receiver/transmitter of the master module to space parity;

initializing a second receiver/transmitter of the master module to mark parity;

determining whether a first byte of a message is a command byte or a data byte;

if the first byte is a data byte, transmitting the first byte to the at least one slave module using the first receiver/transmitter; and

if the first byte is a command byte, transmitting the first byte to the at least one slave module using the second receiver/transmitter.

2. A method in accordance with claim 1, further comprising determining an address of the at least one slave module.

3. A method in accordance with claim 2, further comprising transmitting an address byte to the at least one slave module, the address byte including the address of the at least one slave module.

4. A method in accordance with claim 1, wherein initializing a first receiver/transmitter comprises setting a parity bit to zero.

5. A method in accordance with claim 4, wherein initializing a second receiver/transmitter comprises setting a parity bit to one.

6. A method in accordance with claim 1, wherein determining whether a first byte of a message is a command byte or a data byte comprises detecting a final bit of the first byte.

7. A method in accordance with claim 1, further comprising determining whether the message includes additional bytes to be transmitted to the at least one slave module.

8. A serial communication system comprising:

a plurality of slave modules; and

a master module comprising a first port and a second port, each of said first port and said second port coupled to each of said plurality of slave modules, said master module configured to;

initialize said first port to space parity;

initialize said second port to mark parity;

transmit at least one data byte to at least one of said plurality of slave modules via said first port; and

transmit at least one command byte to at least one of said plurality of slave modules via said second port.

9. A serial communication system in accordance with claim 8, wherein said master module further comprises a memory configured to store an address associated with each slave module.

10. A serial communication system in accordance with claim 9, wherein said master module is further configured to determine an address associated with a specified slave module of said plurality of slave modules.

11. A serial communication system in accordance with claim 10, wherein said master module is further configured to transmit an address byte to said plurality of slave modules, the address byte including the address of said specified slave module.

12. A serial communication system in accordance with claim 8, wherein said master module is further configured to determine a byte type within a message based on a last bit of each byte.

13. A serial communication system in accordance with claim 8, wherein said master module is further configured to:

transmit an initial byte of a message to a specified slave module of said plurality of slave modules via one of said first port and said second port; and

determine whether the message includes additional bytes to be transmitted to said specified slave module.

14. A master device for use with a communication network, said master device comprising:

a multiport communication module comprising;

a first universal asynchronous receiver/transmitter (UART) coupled to a plurality of slave modules via a network;

a second UART coupled to the plurality of slave modules via the network; and

a microprocessor coupled to said first UART and said second UART via a bus, said microprocessor configured to;

initialize said first UART to space parity;

initialize said second UART to mark parity;

transmit at least one data byte within a message to at least one of the plurality of slave modules via said first UART; and

transmit at least one command byte within the message to at least one of the plurality of slave modules via said second UART.

15. A master device in accordance with claim 14, further comprising a memory configured to store an address associated with each slave module.

16. A master device in accordance with claim 15, wherein said microprocessor is further configured to determine an address associated with a specified slave module of the plurality of slave modules.

17. A master device in accordance with claim 16, wherein said microprocessor is further configured to transmit an address byte to the plurality of slave modules, the address byte including the address of the specified slave module.

18. A master device in accordance with claim 14, wherein said microprocessor is further configured to:

initialize said first UART by setting a parity bit to zero; and

initialize said second UART by setting a parity bit to one.

19. A master device in accordance with claim 14, wherein said microprocessor is further configured to determine a byte type for each byte within the message based on a last bit of each byte.

20. A master device in accordance with claim 14, wherein said microprocessor is further configured to:

transmit an initial byte of the message to a specified slave module of the plurality of slave modules via one of said first UART and said second UART; and

determine whether the message includes additional bytes to be transmitted to the specified slave module.