SHIFT REGISTER CIRCUIT

• US 20110142192A1
• Filed: 12/03/2010
• Published: 06/16/2011
• Est. Priority Date: 12/11/2009
• Status: Active Grant

• Current Assignee: AU Optronics Corporation
• Original Assignee: AU Optronics Corporation
• Inventors: Yang, Yu-Chung, Lin, Kun-Yueh, Hsu, Kuo-Hua, Lin, Chih-Ying
• Granted Patent: US 8,204,170 B2
• Time in Patent Office: Days
• US Class Current: 377/77
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G11C 19/00 Digital stores in which the information is moved stepwise, e.g. shift registers
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence

Abstract

A shift register circuit includes plural shift register stages for providing plural gate signals. Each shift register stage includes a pull-up unit, a pull-up control unit, an input unit, a first pull-down unit, a second pull-down unit, and a pull-down control unit. The pull-up control unit generates a first control signal according to a driving control voltage and a first clock. The pull-up unit pulls up a corresponding gate signal according to the first control signal. The input unit is utilized for inputting the gate signal of a preceding shift register stage to become the driving control voltage according to a second clock having a phase opposite to the first clock. The pull-down control unit generates a second control signal according to the driving control voltage. The first and second pull-down units pull down the corresponding gate signal and the first control signal respectively according to the second control signal.

Claims

1. A shift register circuit for providing plural gate signals to plural gate lines, the shift register circuit comprising a plurality of shift register stages, an Nth shift register stage of the shift register stages comprising:

a pull-up unit, electrically connected to an Nth gate line of the gate lines, for pulling up an Nth gate signal of the gate signals according to a first control signal and a high power voltage;

a pull-up control unit, electrically connected to the pull-up unit, for generating the first control signal according to a driving control voltage and a first clock;

an input unit, electrically connected to the pull-up control unit and an (N−

1) th shift register stage of the shift register stages, for inputting an (N−

1) th gate signal of the gate signals to become the driving control voltage according to an input control signal;

an energy-store unit, electrically connected to the pull-up control unit and the input unit, for performing a charging process or a discharging process based on the (N−

1)th gate signal;

a first pull-down unit, electrically connected to the Nth gate line and the pull-up unit, for pulling down the Nth gate signal according to a second control signal;

a pull-down control unit, electrically connected to the input unit and the first pull-down unit, for generating the second control signal according to the driving control voltage and the high power voltage; and

a second pull-down unit, electrically connected to the pull-down control unit and the pull-up control unit, for pulling down the first control signal according to the second control signal.

2. The shift register circuit of claim 1, further comprising:

an input control unit, electrically connected to the input unit, for inputting a second clock to become the input control signal according to the high power voltage, wherein the second clock has a phase opposite to the first clock.

3. The shift register circuit of claim 2, wherein:

the input unit comprises a first transistor, the first transistor comprising;

a first end electrically connected to the (N−

1) th shift register stage for receiving the (N−

1)th gate signal;

a gate end for receiving the input control signal; and

a second end electrically connected to the pull-up control unit, the pull-down control unit and the energy-store unit;

the input control unit comprises a second transistor, the second transistor comprising;

a first end for receiving the second clock;

a gate end for receiving the high power voltage; and

a second end, electrically connected to the gate end of the first transistor, for providing the input control signal;

the pull-up unit comprises a third transistor, the third transistor comprising;

a first end for receiving the high power voltage;

a gate end electrically connected to the pull-up control unit for receiving the first control signal; and

a second end electrically connected to the Nth gate line and the first pull-down unit; and

the first pull-down unit comprises a fourth transistor, the fourth transistor comprising;

a first end electrically connected to the Nth gate line;

a gate end electrically connected to the pull-down control unit for receiving the second control signal; and

a second end for receiving a low power voltage.

4. The shift register circuit of claim 1, wherein:

the second pull-down unit comprises a first transistor, the first transistor comprising;

a first end electrically connected to the pull-up control unit and the pull-up unit;

a gate end electrically connected to the pull-down control unit for receiving the second control signal; and

a second end for receiving a low power voltage;

the pull-up control unit comprises;

a second transistor comprising a first end for receiving the first clock, a gate end electrically connected to the input unit for receiving the driving control voltage, and a second end; and

a third transistor comprising a first end electrically connected to the gate end of the second transistor, a gate end electrically connected to the second end of the second transistor, and a second end electrically connected to the pull-up unit and the first end of the first transistor; and

the energy-store unit comprises a capacitor electrically connected between the gate and second ends of the second transistor.

5. The shift register circuit of claim 4, wherein the third transistor is an amorphous-Si thin film transistor, and a width/length ratio of the amorphous-Si thin film transistor is greater than that of the first transistor.

6. The shift register circuit of claim 1, wherein the pull-down control unit comprises:

a first transistor comprising a first end for receiving the high power voltage, a gate end electrically connected to the first end, and a second end electrically connected to the first and second pull-down units; and

a second transistor comprising a first end electrically connected to the second end of the first transistor, a gate end electrically connected to the input unit for receiving the driving control voltage, and a second end for receiving a low power voltage.

7. The shift register circuit of claim 1, wherein the pull-down control unit comprises:

a first transistor comprising a first end for receiving the high power voltage, a second end electrically connected to the first and second pull-down units, and a gate end;

a second transistor comprising a first end electrically connected to the second end of the first transistor, a gate end electrically connected to the input unit for receiving the driving control voltage, and a second end for receiving a low power voltage;

a third transistor comprising a first end for receiving the high power voltage, a gate end electrically connected to the first end of the third transistor, and a second end electrically connected to the gate end of the first transistor; and

a fourth transistor comprising a first end electrically connected to the second end of the third transistor, a gate end electrically connected to the input unit for receiving the driving control voltage, and a second end for receiving the low power voltage.

8. The shift register circuit of claim 1, wherein:

the energy-store unit performs the charging process based on the (N−

1) th gate signal when the input unit inputs the (N−

1) th gate signal having high voltage level to become the driving control voltage according to the input control signal; and

the energy-store unit performs the discharging process based on the (N−

1)th gate signal when the input unit inputs the (N−

1)th gate signal having low voltage level to become the driving control voltage according to the input control signal.

9. A shift register circuit for providing plural gate signals to plural gate lines, the shift register circuit comprising a plurality of shift register stages, an Nth shift register stage of the shift register stages comprising:

a pull-up unit, electrically connected to an Nth gate line of the gate lines, for pulling up an Nth gate signal of the gate signals according to a first control signal and a low-frequency clock;

a pull-up control unit, electrically connected to the pull-up unit, for generating the first control signal according to a driving control voltage and a first clock;

a first clock input unit, electrically connected to the pull-up control unit, for inputting the first clock to the pull-up control unit according to the low-frequency clock;

an input unit, electrically connected to the pull-up control unit and an (N−

1) th shift register stage of the shift register stages, for inputting an (N−

1) th gate signal of the gate signals to become the driving control voltage according to an input control signal;

an input control unit, electrically connected to the input unit, for inputting a second clock to become the input control signal according to the low-frequency clock, wherein the second clock has a phase opposite to the first clock;

a second clock input unit, electrically connected to the input control unit, for inputting the second clock to the input control unit according to the low-frequency clock;

an energy-store unit, electrically connected to the pull-up control unit and the input unit, for performing a charging process or a discharging process based on the (N−

1)th gate signal;

a first pull-down unit, electrically connected to the Nth gate line and the pull-up unit, for pulling down the Nth gate signal according to a second control signal;

a pull-down control unit, electrically connected to the input unit and the first pull-down unit, for generating the second control signal according to the driving control voltage and the low-frequency clock; and

a second pull-down unit, electrically connected to the pull-down control unit and the pull-up control unit, for pulling down the first control signal according to the second control signal.

10. The shift register circuit of claim 9, wherein:

a frequency of the low-frequency clock is less than a frequency of the first clock.

11. The shift register circuit of claim 9 wherein:

the second clock input unit comprises;

a first transistor comprising a first end for receiving the second clock, a second end electrically connected to the input control unit, and a gate end; and

a second transistor comprising a first end for receiving the low-frequency clock, a gate end electrically connected to the first end of the second transistor, and a second end electrically connected to the gate end of the first transistor;

the input unit comprises a third transistor, the third transistor comprising;

a first end electrically connected to the (N−

1) th shift register stage for receiving the (N−

1)th gate signal;

a gate end for receiving the input control signal; and

a second end electrically connected to the pull-up control unit, the pull-down control unit and the energy-store unit;

the input control unit comprises a fourth transistor, the fourth transistor comprising;

a first end electrically connected to the second end of the first transistor;

a gate end for receiving the low-frequency clock; and

a second end, electrically connected to the gate end of the third transistor, for providing the input control signal;

the first clock input unit comprises;

a fifth transistor comprising a first end for receiving the first clock, a second end electrically connected to the pull-up control unit, and a gate end; and

a sixth transistor comprising a first end for receiving the low-frequency clock, a gate end electrically connected to the first end of the sixth transistor, and a second end electrically connected to the gate end of the fifth transistor;

the pull-up control unit comprises;

a seventh transistor comprising a first end electrically connected to the second end of the fifth transistor, a gate end electrically connected to the input unit for receiving the driving control voltage, and a second end; and

an eighth transistor comprising a first end electrically connected to the gate end of the seventh transistor, a gate end electrically connected to the second end of the seventh transistor, and a second end electrically connected to the pull-up unit and the second pull-down unit;

the second pull-down unit comprises a ninth transistor, the ninth transistor comprising;

a first end electrically connected to the second end of the eighth transistor;

a gate end electrically connected to the pull-down control unit for receiving the second control signal; and

a second end for receiving a low power voltage; and

the energy-store unit comprises a capacitor electrically connected between the gate and second ends of the seventh transistor.

12. The shift register circuit of claim 11, wherein the eighth transistor is an amorphous-Si thin film transistor, and a width/length ratio of the amorphous-Si thin film transistor is greater than that of the ninth transistor.

13. The shift register circuit of claim 9, wherein:

the pull-up unit comprises a first transistor, the first transistor comprising;

a first end for receiving the low-frequency clock;

a gate end electrically connected to the pull-up control unit for receiving the first control signal; and

a second end electrically connected to the Nth gate line and the first pull-down unit; and

the first pull-down unit comprises a second transistor, the second transistor comprising;

a first end electrically connected to the Nth gate line;

a gate end electrically connected to the pull-down control unit for receiving the second control signal; and

a second end for receiving a low power voltage.

14. The shift register circuit of claim 9, wherein the pull-down control unit comprises:

a first transistor comprising a first end for receiving the low-frequency clock, a gate end electrically connected to the first end, and a second end electrically connected to the first and second pull-down units; and

a second transistor comprising a first end electrically connected to the second end of the first transistor, a gate end electrically connected to the input unit for receiving the driving control voltage, and a second end for receiving a low power voltage.

15. The shift register circuit of claim 9, wherein the pull-down control unit comprises:

a first transistor comprising a first end for receiving the low-frequency clock, a second end electrically connected to the first and second pull-down units, and a gate end;

a second transistor comprising a first end electrically connected to the second end of the first transistor, a gate end electrically connected to the input unit for receiving the driving control voltage, and a second end for receiving a low power voltage;

a third transistor comprising a first end for receiving the low-frequency clock, a gate end electrically connected to the first end of the third transistor, and a second end electrically connected to the gate end of the first transistor; and

a fourth transistor comprising a first end electrically connected to the second end of the third transistor, a gate end electrically connected to the input unit for receiving the driving control voltage, and a second end for receiving the low power voltage.

16. The shift register circuit of claim 9, wherein:

the energy-store unit performs the charging process based on the (N−

1) th gate signal when the input unit inputs the (N−

1) th gate signal having high voltage level to become the driving control voltage according to the input control signal; and

the energy-store unit performs the discharging process based on the (N−

1)th gate signal when the input unit inputs the (N−

1)th gate signal having low voltage level to become the driving control voltage according to the input control signal.

17. A shift register circuit for providing plural gate signals to plural gate lines, the shift register circuit comprising a plurality of shift register stages, an Nth shift register stage of the shift register stages comprising:

a pull-up unit, electrically connected to an Nth gate line of the gate lines, for pulling up an Nth gate signal of the gate signals according to a first control signal and a low-frequency clock;

a pull-up control unit, electrically connected to the pull-up unit, for generating the first control signal according to a driving control voltage and a first clock;

an input unit, electrically connected to the pull-up control unit and an (N−

1) th shift register stage of the shift register stages, for inputting an (N−

1) th gate signal of the gate signals to become the driving control voltage according to an input control signal;

an input control unit, electrically connected to the input unit, for inputting a second clock to become the input control signal according to the low-frequency clock, wherein the second clock has a phase opposite to the first clock;

an energy-store unit, electrically connected to the pull-up control unit and the input unit, for performing a charging process or a discharging process based on the (N−

1)th gate signal;

a first pull-down unit, electrically connected to the Nth gate line and an (N+1) th shift register stage of the shift register stages, for pulling down the Nth gate signal according to an (N+1)th gate signal of the gate signals;

a second pull-down unit, electrically connected to the pull-up control unit, for pulling down the first control signal according to a second control signal;

a first pull-down control unit, electrically connected to the input unit and the second pull-down unit, for generating the second control signal according to the driving control voltage and a first low-frequency clock;

a third pull-down unit, electrically connected to the pull-up control unit, for pulling down the first control signal according to a third control signal; and

a second pull-down control unit, electrically connected to the input unit and the third pull-down unit, for generating the third control signal according to the driving control voltage and a second low-frequency clock having a phase opposite to the first low-frequency clock.

18. The shift register circuit of claim 17, wherein:

a frequency of the first low-frequency clock is less than a frequency of the first clock; and

a frequency of the low-frequency clock is less than a frequency of the first clock.

19. The shift register circuit of claim 17, wherein:

the energy-store unit performs the charging process based on the (N−

1) th gate signal when the input unit inputs the (N−

1) th gate signal having high voltage level to become the driving control voltage according to the input control signal; and

the energy-store unit performs the discharging process based on the (N−

1)th gate signal when the input unit inputs the (N−

1)th gate signal having low voltage level to become the driving control voltage according to the input control signal.

20. The shift register circuit of claim 17, wherein:

the first pull-down control unit comprises;

a first transistor comprising a first end for receiving the first low-frequency clock, a second end electrically connected to the second pull-down unit, and a gate end;

a second transistor comprising a first end electrically connected to the second end of the first transistor, a gate end electrically connected to the input unit for receiving the driving control voltage, and a second end for receiving a low power voltage;

a third transistor comprising a first end for receiving the first low-frequency clock, agate end electrically connected to the first end of the third transistor, and a second end electrically connected to the gate end of the first transistor;

a fourth transistor comprising a first end electrically connected to the second end of the third transistor, a gate end electrically connected to the input unit for receiving the driving control voltage, and a second end for receiving the low power voltage; and

the second pull-down control unit comprises;

a fifth transistor comprising a first end for receiving the second low-frequency clock, a second end electrically connected to the third pull-down unit, and a gate end;

a sixth transistor comprising a first end electrically connected to the second end of the fifth transistor, a gate end electrically connected to the input unit for receiving the driving control voltage, and a second end for receiving a low power voltage;

a seventh transistor comprising a first end for receiving the second low-frequency clock, a gate end electrically connected to the first end of the seventh transistor, and a second end electrically connected to the gate end of the fifth transistor; and

an eighth transistor comprising a first end electrically connected to the second end of the seventh transistor, agate end electrically connected to the input unit for receiving the driving control voltage, and a second end for receiving the low power voltage.

21. The shift register circuit of claim 17, wherein:

the input unit comprises a first transistor, the first transistor comprising;

a first end electrically connected to the (N−

1) th shift register stage for receiving the (N−

1)th gate signal;

a gate end for receiving the input control signal; and

a second end electrically connected to the pull-up control unit, the first pull-down control unit, the second pull-down control unit and the energy-store unit; and

the input control unit comprises a second transistor, the second transistor comprising;

a first end for receiving the second clock;

a gate end for receiving the low-frequency clock; and

a second end, electrically connected to the gate end of the first transistor, for providing the input control signal.

22. The shift register circuit of claim 17, wherein:

the pull-up control unit comprises;

a first transistor comprising a first end for receiving the first clock, a gate end electrically connected to the input unit for receiving the driving control voltage, and a second end; and

a second transistor comprising a first end electrically connected to the gate end of the first transistor, a gate end electrically connected to the second end of the first transistor, and a second end electrically connected to the pull-up unit, the second pull-down unit and the third pull-down unit;

the first pull-down unit comprises a third transistor, the third transistor comprising;

a first end electrically connected to the Nth gate line;

a gate end electrically connected to the (N+1) th shift register stage for receiving the (N+1)th gate signal; and

a second end for receiving a low power voltage;

the second pull-down unit comprises a fourth transistor, the fourth transistor comprising;

a first end electrically connected to the second end of the second transistor;

a gate end electrically connected to the first pull-down control unit for receiving the second control signal; and

a second end for receiving the low power voltage;

the third pull-down unit comprises a fifth transistor, the fifth transistor comprising;

a first end electrically connected to the second end of the second transistor;

a gate end electrically connected to the second pull-down control unit for receiving the third control signal; and

a second end for receiving the low power voltage; and

the energy-store unit comprises a capacitor electrically connected between the gate and second ends of the first transistor.

23. The shift register circuit of claim 22, wherein the second transistor is an amorphous-Si thin film transistor, and a width/length ratio of the amorphous-Si thin film transistor is greater than width/length ratios of the fourth and fifth transistors.