EXECUTION OF VARIABLE WIDTH VECTOR PROCESSING INSTRUCTIONS

• US 20110145543A1
• Filed: 12/15/2009
• Published: 06/16/2011
• Est. Priority Date: 12/15/2009
• Status: Active Grant

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Damron, Peter Carl
• Granted Patent: US 8,555,034 B2
• Time in Patent Office: Days
• US Class Current: 712/3
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30076 to perform miscellaneous control operations, e.g. NOP
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/30189 according to execution mode, e.g. mode flag
• CPC Class Codes: G06F 9/3887 controlled by a single instruction for multiple data lanes [SIMD]

Abstract

A processing unit executes a vector width instruction in a program and the processing unit obtains and supplies the width of an appropriate vector register that will be used to process variable vector processing instructions. Then, when the processing unit executes variable vector processing instructions in the program, the processing unit processes the variable vector processing instructions using the appropriate vector register with the instructions having the same width as the appropriate vector register. The width that the processing unit obtains may be less than an actual width of the appropriate vector register and may set by the processing unit. In this way, many different vector widths can be supported using a single set of instructions for vector processing. New instructions are not required if vector widths are changed and processing units having vector registers of differing widths do not require different code.

Claims

1. A system for executing variable width vector processing instructions, comprising:

at least one vector register, operable to store a vector;

at least one processing unit, communicably coupled to the at least one vector register, operable to execute code of at least one program that includes at least one variable vector processing instruction and at least one vector register width instruction and to supply a width of the at least one vector register in response to executing the at least one vector register width instruction;

wherein the at least one processing unit processes the at least one variable vector processing instruction utilizing the at least one vector register with a vector width of the width of the at least one vector register supplied by the at least one processing unit.

2. The system of claim 1, further comprising:

at least one vector register width register that stores the width of the at least one vector register;

wherein the at least one processing unit supplies the width of the at least one vector register from the at least one vector register width register.

3. The system of claim 1, wherein the at least one vector register is comprised of a plurality of registers.

4. The system of claim 1, wherein the at least one processing unit is operable to utilize the at least one vector register as a non-vector register when executing a non-vector instruction.

5. The system of claim 1, wherein the width of the at least one vector register supplied by the at least one processing unit is less than an actual width of the at least one vector register.

6. The system of claim 5, wherein the processing unit is operable to set the width of the at least one vector register as less than the actual width of the at least one vector register.

7. The system of claim 1, wherein the at least one processing unit is operable to align the vector stored in the at least one vector register as part of processing the at least one variable vector processing instruction.

8. The system of claim 1, wherein the at least one variable vector processing instruction comprises at least one of a vector add instruction, a vector subtract instruction, a vector multiply instruction, a vector divide instruction, a vector and instruction, a vector or instruction, or a vector xor instruction.

9. The system of claim 1, wherein the at least one variable vector processing instruction comprises at least one of a vector rotate instruction, a vector load instruction, a vector store instruction, a vector element extraction instruction, a scalar expansion instruction, or a vector reduction instruction.

10. The system of claim 1, further comprising:

at least one tangible storage media, communicably coupled to the at least one processing unit, that stores the code of the at least one program.

11. A method for variable length vector operation instruction processing, comprising:

obtaining a width of at least one vector register during execution of code of a program utilizing at least one processing unit by executing at least one vector register width instruction in the code;

executing at least one variable vector processing instruction in the code utilizing the at least one processing unit; and

processing the at least one variable vector processing instruction utilizing the at least one vector register with a vector width of the obtained width of the at least one vector register.

12. The method of claim 11, wherein said obtaining a width of at least one vector register during execution of code of a program utilizing at least one processing unit by executing at least one vector register width instruction in the code comprises:

obtaining the width of the vector register from at least one vector register width register of the at least one processing unit that stores the width of the vector register.

13. The method of claim 11, wherein the width of the at least one vector register is less than an actual width of the at least one vector register, further comprising:

setting the width of the at least one vector register as less than the actual width of the at least one vector register utilizing the at least one processing unit.

14. The method of claim 11, wherein the at least one variable vector processing instruction comprises at least one of a vector add instruction, a vector subtract instruction, a vector multiply instruction, a vector divide instruction, a vector and instruction, a vector or instruction, or a vector xor instruction.

15. The method of claim 11, wherein the at least one variable vector processing instruction comprises at least one of a vector rotate instruction, a vector load instruction, a vector store instruction, a vector element extraction instruction, a scalar expansion instruction, or a vector reduction instruction.

16. The method of claim 11, wherein said processing the at least one variable vector processing instruction utilizing the at least one vector register with a vector width of the obtained width of the at least one vector register comprises:

aligning a vector stored in the at least one vector register.

17. The method of claim 11, further comprising:

utilizing the at least one vector register as a non-vector register when executing a non-vector instruction utilizing the at least one processing unit.

18. The method of claim 11, further comprising:

executing the code utilizing at least one additional processor including at least one additional vector register that has a different width than the at least one vector register.

19. The method of claim 11, further comprising:

inserting the at least one vector register width instruction and the at least one variable vector processing instruction in the code during compilation.

20. A computer program product, comprising:

a first set of instructions, stored in at least one computer readable storage medium, executable by at least one processing unit to obtain a width of at least one vector register during execution of code of a program by executing at least one vector register width instruction in the code; and

a second set of instructions, stored in the at least one computer readable storage medium, executable by the at least one processing unit to execute at least one variable vector processing instruction in the code and process the at least one variable vector processing instruction utilizing the at least one vector register with a vector width of the obtained width of the at least one vector register.