TROUBLE ANALYSIS APPARATUS

• US 20110145647A1
• Filed: 08/04/2009
• Published: 06/16/2011
• Est. Priority Date: 08/04/2008
• Status: Active Grant

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Higuchi, Junichi, Yoshikawa, Takashi, Hidaka, Youichi
• Granted Patent: US 8,635,496 B2
• Time in Patent Office: Days
• US Class Current: 714/37
• CPC Class Codes: G06F 11/0706 the processing taking place on a specific hardware platform or in a specific software environment
• CPC Class Codes: G06F 11/079 Root cause analysis, i.e. error or fault diagnosis in a hardware test environment G06F11/22; in a software test environment G06F11/36

Abstract

A trouble analysis apparatus is provided which includes: a system topology storing portion; an error detection information receiving portion which collects error detection information; and a trouble source determination portion which, based on both the error detection information collected by the error detection information receiving portion and system topology information stored in the system topology information storing portion, determines a trouble source functional element that is presumed as a functional element which is a source of a system trouble. Links included in the system topology information have information indicating spreading directions of error operations between the functional elements when trouble occurs. When the trouble source detection portion receives the error detection information with regard to multiple error functional elements, the trouble source determination portion sequentially selects one of the multiple error functional elements. The trouble source detection portion determines whether or not directions from the selected error functional element to other error functional elements conform to the spreading directions included in the system topology information. The trouble source determination portion determines the selected error functional element as the trouble source functional element when the spreading directions are conformable.

Claims

1. A trouble analysis apparatus of a computer system constituted from functional elements including hardware and software, comprising:

a system topology information storing portion storing system topology information which includes both information of the functional elements and information of links between the functional elements that indicates spreading directions of error operations between the functional elements upon trouble;

an error detection information receiving portion collecting error detection information regarding error functional elements that are the functional elements in which error operations are indicated; and

a trouble source determination portion which, based on the error detection information and the system topology information, determines a trouble source functional element from the functional elements that is presumed as a source of the trouble.

2. A trouble analysis apparatus according to claim 1, wherein

when the error functional element is plural, the trouble source determination portion sequentially selects one of the plurality of error functional elements, and

when spreading directions of error operations from the selected error functional element to other error functional elements conform to the spreading directions included in the system topology information, the trouble source determination portion determines the selected error functional element as the trouble source functional element.

3. A trouble analysis apparatus according to claim 1, further comprising

a trouble topology information generation portion which, in reference to the system topology information, generates trouble topology information constituted from both the multiple error functional elements and links between the multiple error functional elements, wherein

when spreading directions of error operations from the selected error functional element to other error functional elements conform to the spreading directions included in the error topology information, the trouble source determination portion determines the selected error functional element as the trouble source functional element.

4. A trouble analysis apparatus according to claim 1, further comprising:

a basic topology information storing portion which, with regard to each layer included in each apparatus that constitutes the computer system, stores basic topology information constituted from both the functional elements included in the layer and links between the functional elements included in the layer; and

a system topology information generation portion which, in reference to both information that indicates configuration of the computer system and the basic topology information, generates the system topology information.

5. A trouble analysis apparatus according to claim 1, wherein

the system topology information generation portion updates the system topology information by using a tree structure in reference to the plurality of error functional elements.

6. A computer program stored in a computer readable storage medium conducting a trouble analysis in a computer system which is constituted from functional elements including both hardware and software, comprising instructions for:

generating topology information which includes both information of the functional elements and information of links between the functional elements that indicates spreading directions of error operations between the functional elements upon trouble;

collecting error detection information regarding error functional elements that are the functional elements in which error operations are indicated; and

determining a trouble source functional element from the functional elements that is presumed as a source of the trouble based on the error detection information and the system topology information.

7. A trouble analysis method of a computer system which is constituted from functional elements including both hardware and software, comprising steps of:

generating topology information which includes both information of the functional elements and information of links between the functional elements that indicates spreading directions of error operations between the functional elements upon trouble;

collecting error detection information regarding error functional elements that are the functional elements in which error operations are indicated; and

determining a trouble source functional element from the functional elements that is presumed as a source of the trouble based on the error detection information and the system topology information.