SEMICONDUCTOR DEVICE

• US 20110147737A1
• Filed: 12/13/2010
• Published: 06/23/2011
• Est. Priority Date: 12/18/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kato, Kiyoshi, Koyama, Jun, Yamazaki, Shunpei
• Granted Patent: US 8,610,187 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 12/0335 Making a connection between the transistor and the capacitor, e.g. plug
• CPC Class Codes: H10B 12/30 DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A first transistor including a channel formation region, a first gate insulating layer, a first gate electrode, and a first source electrode and a first drain electrode; a second transistor including an oxide semiconductor layer, a second source electrode and a second drain electrode, a second gate insulating layer, and a second gate electrode; and a capacitor including one of the second source electrode and the second drain electrode, the second gate insulating layer, and an electrode provided to overlap with one of the second source electrode and the second drain electrode over the second gate insulating layer are provided. The first gate electrode and one of the second source electrode and the second drain electrode are electrically connected to each other.

Claims

1. A semiconductor device comprising:

a first transistor comprising;

a channel formation region;

a first impurity region and a second impurity region with the channel formation region interposed between the first impurity region and the second impurity region;

a first insulating layer over the channel formation region;

a first gate electrode over the channel formation region with the first insulating layer interposed therebetween;

a first electrode electrically connected to the first impurity region; and

a second electrode electrically connected to the second impurity region;

a second transistor comprising;

an oxide semiconductor layer;

a third electrode and a fourth electrode, each of the third electrode and the fourth electrode electrically connected to the oxide semiconductor layer;

a second insulating layer over the oxide semiconductor layer, the third electrode, and the fourth electrode; and

a second gate electrode overlapping the oxide semiconductor layer with the second insulating layer interposed therebetween;

a capacitor element comprising;

the third electrode;

the second insulating layer; and

a fifth electrode overlapping the third electrode with the second insulating layer interposed therebetween,

wherein the first gate electrode and the third electrode are electrically connected to each other.

2. A semiconductor device comprising:

a first gate electrode over a semiconductor with a first insulating layer interposed therebetween;

a second insulating layer over the first gate electrode;

a first electrode and a second electrode over the second insulating layer;

an oxide semiconductor layer over the second insulating layer and electrically connected to the first electrode and the second electrode;

a third insulating layer over the first electrode, the second electrode, and the oxide semiconductor layer;

a third electrode over the first electrode with the third insulating layer interposed therebetween; and

a second gate electrode over the oxide semiconductor layer with the third insulating layer interposed therebetween,

wherein the first gate electrode and the first electrode are electrically connected to each other.

3. The semiconductor device according to claim 2, wherein the semiconductor is a semiconductor substrate.

4. The semiconductor device according to claim 2, further comprising a sidewall insulator in contact with a side of the first gate electrode.

5. The semiconductor device according to claim 2,

wherein the semiconductor comprises a first impurity region, a second impurity region, and a channel formation region between the first impurity region and the second impurity region, and

wherein the channel formation region is overlapped with the first gate electrode.

6. The semiconductor device according to claim 2, wherein the oxide semiconductor layer comprises indium and gallium.

7. The semiconductor device according to claim 2, wherein the third electrode overlaps the oxide semiconductor layer.

8. The semiconductor device according to claim 2, further comprising a fourth insulating layer between the oxide semiconductor layer and the first electrode,

wherein the fourth insulating layer comprises an opening at a region overlapped with the third electrode, and

wherein the oxide semiconductor layer is provided in the opening.

9. The semiconductor device according to claim 2, wherein the oxide semiconductor layer and each of the first electrode and the second electrode are in direct contact with each other at a top surface of the oxide semiconductor layer.

10. An electronic appliance comprising the semiconductor device according to claim 2, wherein the electronic appliance is one selected from the group consisting of a computer, a mobile phone, a personal digital assistant, a digital camera, a digital video camera, an electronic paper, and a television.

11. A memory device comprising the semiconductor device according to claim 2.