SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

• US 20110147738A1
• Filed: 12/15/2010
• Published: 06/23/2011
• Est. Priority Date: 12/18/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: KOEZUKA, Junichi, YAMAZAKI, Shunpei
• Granted Patent: US 9,240,488 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 21/425 producing ion implantation
• CPC Class Codes: H01L 21/426 using masks
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A transistor including an oxide semiconductor, which has good on-state characteristics, and a high-performance semiconductor device including a transistor capable of high-speed response and high-speed operation. In the transistor including an oxide semiconductor, oxygen-defect-inducing factors are introduced (added) into an oxide semiconductor layer, whereby the resistance of a source and drain regions are selectively reduced. Oxygen-defect-inducing factors are introduced into the oxide semiconductor layer, whereby oxygen defects serving as donors can be effectively formed in the oxide semiconductor layer. The introduced oxygen-defect-inducing factors are one or more selected from titanium, tungsten, and molybdenum, and are introduced by an ion implantation method.

Claims

1. A semiconductor device comprising:

an oxide semiconductor layer including a channel formation region and source and drain regions;

a gate insulating layer over the oxide semiconductor layer;

a gate electrode layer over the gate insulating layer;

an insulating layer over the gate electrode layer; and

a source electrode layer and a drain electrode layer over the insulating layer,

wherein the source and drain regions include oxygen-defect-inducing factors.

2. The semiconductor device according to claim 1,

wherein the channel formation region includes oxygen-defect-inducing factors.

3. The semiconductor device according to claim 1,

wherein the gate electrode overlaps with the channel formation region,

wherein the insulating layer covers the oxide semiconductor layer, the gate insulating layer, and the gate electrode layer, and

wherein the source electrode layer is electrically connected to the source region and the drain electrode layer is electrically connected to the drain region.

4. The semiconductor device according to claim 1, wherein the oxygen-defect-inducing factors are one or more selected from the group consisting of titanium, tungsten, and molybdenum.

5. A semiconductor device comprising:

an oxide semiconductor layer including a channel formation region, a first region, and a second region over a substrate;

a gate insulating layer over the oxide semiconductor layer;

a gate electrode layer overlapping over the gate insulating layer;

an insulating layer over the gate electrode layer; and

a source electrode layer and a drain electrode layer over the insulating layer,

wherein the first region is a source and drain regions, and

wherein the first region and the second region include oxygen-defect-inducing factors,

wherein the second region is provided between the channel formation region and the first region and has higher resistance than the first region.

6. The semiconductor device according to claim 5,

wherein the channel formation region includes oxygen-defect-inducing factors.

7. The semiconductor device according to claim 5,

wherein the gate electrode overlaps with the channel formation region,

wherein the insulating layer covers the oxide semiconductor layer, the gate insulating layer, and the gate electrode layer, and

wherein the source electrode layer is electrically connected to the source region and the drain electrode layer is electrically connected to the drain region.

8. The semiconductor device according to claim 5, wherein the second region has higher concentration of the oxygen-defect-inducing factors than the first region.

9. The semiconductor device according to claim 5, wherein the oxygen-defect-inducing factors are one or more selected from the group consisting of titanium, tungsten, and molybdenum.

10. A method for manufacturing a semiconductor device, comprising the steps of:

forming an oxide semiconductor layer over a substrate;

forming a gate insulating layer over the oxide semiconductor layer;

forming a gate electrode layer over the gate insulating layer;

forming a channel formation region, a source region, and a drain region in the oxide semiconductor layer by performing treatment of introducing oxygen-defect-inducing factors on the oxide semiconductor layer for selectively forming oxygen defects;

forming an insulating layer over the gate electrode layer; and

forming a source electrode layer and a drain electrode layer over the insulating layer.

11. The method for manufacturing a semiconductor device, according to claim 10, wherein the channel formation region includes oxygen-defect-inducing factors in the step of introducing the oxygen-defect-inducing factors.

12. The method for manufacturing a semiconductor device, according to claim 10, wherein the oxygen-defect-inducing factors are introduced by an ion implantation method.

13. The method for manufacturing a semiconductor device, according to claim 10, wherein the oxygen-defect-inducing factors are one or more selected from the group consisting of titanium, tungsten, and molybdenum.

14. A method for manufacturing a semiconductor device, comprising the steps of:

forming an oxide semiconductor layer over a substrate;

forming a gate insulating layer over the oxide semiconductor layer;

forming a gate electrode layer over the gate insulating layer;

forming an insulating layer over the gate electrode layer;

forming a first region functioning as a source and drain regions, a second region having higher resistance than the first region, and a channel formation region by performing treatment of introducing oxygen-defect-inducing factors on the oxide semiconductor layer for selectively forming oxygen defects; and

forming a source electrode layer and a drain electrode layer over the insulating layer.

15. The method for manufacturing a semiconductor device, according to claim 14, wherein the channel formation region includes oxygen-defect-inducing factors in the step of introducing the oxygen-defect-inducing factors.

16. The method for manufacturing a semiconductor device, according to claim 14, wherein the oxygen-defect-inducing factors are introduced by an ion implantation method.

17. The method for manufacturing a semiconductor device, according to claim 14, wherein the oxygen-defect-inducing factors are one or more selected from the group consisting of titanium, tungsten, and molybdenum.