GROWTH OF COINCIDENT SITE LATTICE MATCHED SEMICONDUCTOR LAYERS AND DEVICES ON CRYSTALLINE SUBSTRATES

• US 20110147791A1
• Filed: 12/21/2009
• Published: 06/23/2011
• Est. Priority Date: 12/21/2009
• Status: Active Grant

• Current Assignee: Alliance For Sustainable Energy LLC
• Original Assignee: Alliance For Sustainable Energy LLC
• Inventors: Ptak, Aaron J., Norman, Andrew G.
• Granted Patent: US 8,507,365 B2
• Time in Patent Office: Days
• US Class Current: 257/103
• CPC Class Codes: H01L 21/0237 Materials
• CPC Class Codes: H01L 21/02373 Group 14 semiconducting materials
• CPC Class Codes: H01L 21/0242 Crystalline insulating materials
• CPC Class Codes: H01L 21/02433 Crystal orientation
• CPC Class Codes: H01L 21/02521 Materials
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/02609 Crystal orientation
• CPC Class Codes: H01L 31/036 characterised by their crystalline structure or particular orientation of the crystalline planes
• CPC Class Codes: H01L 31/0725 Multiple junction or tandem solar cells
• CPC Class Codes: H01L 33/16 with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous
• CPC Class Codes: H01L 33/32 containing nitrogen
• CPC Class Codes: Y02E 10/50 Photovoltaic [PV] energy

Abstract

Methods of fabricating a semiconductor layer or device and said devices are disclosed. The methods include but are not limited to providing a substrate having a crystalline surface with a known lattice parameter (a). The method further includes growing a crystalline semiconductor layer on the crystalline substrate surface by coincident site lattice matched epitaxy, without any buffer layer between the crystalline semiconductor layer and the crystalline surface of the substrate. The crystalline semiconductor layer will be prepared to have a lattice parameter (a′) that is related to the substrate lattice parameter (a). The lattice parameter (a′) maybe related to the lattice parameter (a) by a scaling factor derived from a geometric relationship between the respective crystal lattices.

Claims

1. A method of fabricating a semiconductor layer comprising:

providing a substrate having a crystalline surface with a known lattice parameter (a); and

growing a crystalline semiconductor layer on the crystalline substrate surface by coincident site lattice matched epitaxy, without any buffer layer between the crystalline semiconductor layer and the crystalline surface of the substrate, wherein the crystalline semiconductor layer is prepared to have a lattice parameter (a′

) that is related to the lattice parameter (a).

2. The method of fabricating a semiconductor layer of claim 1 further comprising:

providing a substrate having a hexagonal family crystalline structure; and

growing the crystalline semiconductor layer on a {0001} plane of the hexagonal substrate.

3. The method of fabricating a semiconductor layer of claim 2 further comprising growing a crystalline semiconductor layer which has a hexagonal family crystalline structure on the hexagonal family crystalline substrate surface.

4. The method of fabricating a semiconductor layer of claim 3 further comprising growing a Group III-nitride alloy on the {0001} plane of the hexagonal family crystalline substrate.

5. The method of fabricating a semiconductor layer of claim 4 wherein the Group III-nitride alloy is an InGaN alloy.

6. The method of fabricating a semiconductor layer of claim 3 wherein the hexagonal family crystalline lattice of the semiconductor layer is not rotated with respect to the lattice of the hexagonal family crystalline substrate.

7. The method of fabricating a semiconductor layer of claim 6 wherein the relationship between the lattice parameter (a) of the substrate and the lattice parameter (a′

) of the crystalline semiconductor layer is one of (a′

)=(a)/2 and (a′

)=2(a).

8. The method of fabricating a semiconductor layer of claim 3 wherein the hexagonal family crystalline lattice of the semiconductor layer is rotated 30°

with respect to the lattice of the hexagonal family crystalline substrate.

9. The method of fabricating a semiconductor layer of claim 8 wherein the relationship between the lattice parameter (a) of the substrate and the lattice parameter (a′

) of the crystalline semiconductor layer is one of (a′

)=2(a)/√

3, (a′

)=(a)/√

3, (a′

)=(a)√

3 and (a′

)=(a)√

3/2.

10. The method of fabricating a semiconductor layer of claim 2 further comprising growing a crystalline semiconductor layer which has a cubic crystalline lattice on the hexagonal family crystalline substrate surface.

11. The method of fabricating a semiconductor layer of claim 10 further comprising growing one of a Group II-VI semiconductor, a Group III-V semiconductor, a Group IV semiconductor, alloys of group II-VI semiconductors, alloys of group III-V semiconductors, and alloys of Group IV semiconductors on the {0001} plane of the hexagonal family crystalline substrate.

12. The method of fabricating a semiconductor layer of claim 10 wherein the cubic crystalline lattice of the semiconductor layer comprises a face centered cubic lattice.

13. The method of fabricating a semiconductor layer of claim 12 wherein the relationship between the lattice parameter (a) of the hexagonal family substrate and the lattice parameter (a′

) of the cubic crystalline semiconductor layer is one of, (a′

)=2(a)√

2, (a′

)=(a)/√

2, (a′

)=(a)√

6/2, (a′

)=(a)√

6, (a′

)=(a)√

2/√

3 and (a′

)=2(a)√

2/√

3.

14. The method of fabricating a semiconductor layer of claim 1 further comprising:

providing a substrate having a cubic crystal system structure; and

growing the crystalline semiconductor layer on a {111} plane of the cubic substrate.

15. The method of fabricating a semiconductor layer of claim 14 wherein the substrate is MgAl₂O₄ having a spinel structure.

16. The method of fabricating a semiconductor layer of claim 14 wherein the substrate has a diamond cubic structure.

17. The method of fabricating a semiconductor layer of claim 16 wherein the substrate is one of C, Si, Ge, Sn and their alloys.

18. The method of fabricating a semiconductor layer of claim 14 wherein the substrate has a zincblende structure.

19. The method of fabricating a semiconductor layer of claim 18 wherein the substrate is one of a group II-VI semiconductor, a group III-V semiconductor, alloys of group II-VI semiconductors and alloys of group III-V semiconductors.

20. The method of fabricating a semiconductor layer of claim 14 further comprising growing a crystalline semiconductor layer which has a wurtzite crystalline structure.

21. The method of fabricating a semiconductor layer of claim 20 further comprising growing a Group III-nitride alloy on the {111} plane of the cubic substrate.

22. The method of fabricating a semiconductor layer of claim 21 wherein the Group III-nitride alloy is an InGaN alloy.

23. The method of fabricating a semiconductor layer of claim 22 wherein the InGaN alloy is In_0.31Ga_0.69N (w).

24. The method of fabricating a semiconductor layer of claim 23 wherein the substrate is MgAl₂O₄.

25. The method of fabricating a semiconductor layer of claim 20 wherein the wurtzite crystalline lattice of the crystalline semiconductor layer is rotated 30°

with respect to the lattice of the cubic crystalline substrate.

26. The method of fabricating a semiconductor layer of claim 25 wherein the relationship between the lattice parameter (a) of the substrate and the lattice parameter (a′

) of the crystalline semiconductor layer is one of, (a′

)=2(a)/√

6, (a′

)=(a)/√

6, (a′

)=(a)√

3/√

2 and (a′

)=(a)√

3/2√

2.

27. The method of fabricating a semiconductor layer of claim 14 further comprising growing a crystalline semiconductor layer which has a cubic crystalline structure on the {111} plane of the cubic substrate.

28. The method of fabricating a semiconductor layer of claim 27 further comprising growing a crystalline semiconductor layer which has a cubic crystalline structure of the diamond cubic form.

29. The method of fabricating a semiconductor layer of claim 28 wherein the crystalline semiconductor layer is one of a Group IV semiconductor and a Group IV semiconductor alloy.

30. The method of fabricating a semiconductor layer of claim 27 further comprising growing a crystalline semiconductor layer which has a cubic crystalline structure of the zincblende form.

31. The method of fabricating a semiconductor layer of claim 30 wherein the crystalline semiconductor layer is one of a Group II-VI semiconductor, a Group semiconductor, a Group II-VI semiconductor alloy, and a Group semiconductor alloy.

32. The method of fabricating a semiconductor layer of claim 27 wherein the cubic crystalline lattice of the crystalline semiconductor layer is rotated 30°

with respect to the lattice of the cubic crystalline substrate.

33. The method of fabricating a semiconductor layer of claim 32 wherein the relationship between the lattice parameter (a) of the substrate and the lattice parameter (a′

) of the crystalline semiconductor layer is one of (a′

)=(a)√

3/2, (a′

)=(a)√

3, (a′

)=(a)/√

3 and (a′

)=2(a)/√

3.

34. The method of fabricating a semiconductor layer of claim 1 further comprising:

providing a polar substrate; and

growing a polar crystalline semiconductor on the substrate.

35. The method of fabricating a semiconductor layer of claim 1 further comprising:

providing a substrate having a known coefficient of thermal expansion; and

growing a crystalline semiconductor layer on the substrate which has a coefficient of thermal expansion selected to correspond to the substrate coefficient of thermal expansion.

36. A method of fabricating a semiconductor device comprising:

providing a substrate having a crystalline surface with a known lattice parameter (a);

growing a crystalline semiconductor layer on the crystalline substrate surface by coincident site lattice matched epitaxy, without any buffer layer between the crystalline semiconductor layer and the crystalline surface of the substrate, wherein the crystalline semiconductor layer is prepared to have a lattice parameter (a′

) that is related to the lattice parameter (a); and

epitaxially growing one or more subsequent crystalline semiconductor layers on the first crystalline semiconductor layer.

37. The method of fabricating a semiconductor device of claim 36 further comprising growing a subsequent crystalline semiconductor layers on the crystalline semiconductor layer by coincident site lattice matched epitaxy, without any buffer layer between the subsequent crystalline semiconductor layer and the crystalline semiconductor layer, wherein the subsequent crystalline semiconductor layer is prepared to have a lattice parameter (a′

)′

that is related to the lattice parameter (a′

).

38. The method of fabricating a semiconductor device of claim 37 wherein the crystalline lattice of the subsequent semiconductor layer is rotated 30°

with respect to the lattice of the crystalline semiconductor layer.

39. An electronic device comprising:

a substrate having a crystalline surface with a known lattice parameter (a);

a crystalline semiconductor layer grown on the crystalline substrate surface by coincident site lattice matched epitaxy, without any buffer layer between the crystalline semiconductor layer and the crystalline surface of the substrate, wherein the crystalline semiconductor layer is prepared to have a lattice parameter (a′

) that is related to the lattice parameter (a).

40. The electronic device of claim 39 wherein the lattice of the crystalline semiconductor layer is rotated 30°

with respect to the lattice of the substrate.

41. The electronic device of claim 39 wherein the device is a solid state lighting device comprising:

a substrate having a cubic crystal system structure; and

a crystalline semiconductor layer having a wurtzite crystalline structure.

42. The electronic device of claim 41 wherein the crystalline semiconductor layer comprises a Group III-nitride alloy.

43. The electronic device of claim 42 wherein the substrate comprises MgAl₂O₄ and the crystalline semiconductor layer comprises In_0.31Ga_0.69N (w).

44. The electronic device of claim 42 wherein the substrate comprises Si or GaP and the crystalline semiconductor layer comprises In_0.38Ga_0.62N (w).

45. The electronic device of claim 40 wherein the device is a multiple junction solar cell comprising:

a substrate having a cubic crystal system structure; and

a crystalline semiconductor layer having a cubic crystalline structure.

46. The electronic device of claim 45 wherein the substrate comprises one of a Group IV semiconductor, a Group III-V semiconductor, a Group II-VI semiconductor, a Group IV semiconductor alloy, a Group III-V semiconductor alloy, and a Group II-VI semiconductor alloy and the crystalline semiconductor layer comprises one of a Group IV semiconductor, a Group III-V semiconductor, a Group II-VI semiconductor, a Group IV semiconductor alloy, a Group III-V semiconductor alloy, and a Group II-VI semiconductor alloy.

47. The electronic device of claim 40 wherein the device is a multiple junction solar cell comprising:

a substrate having a cubic crystal system structure; and

a crystalline semiconductor layer having a hexagonal crystalline structure.

48. The electronic device of claim 47 wherein the substrate comprises one of a Group IV semiconductor, a Group III-V semiconductor, a Group II-VI semiconductor, a Group IV semiconductor alloy, a Group III-V semiconductor alloy, and a Group II-VI semiconductor alloy and the crystalline semiconductor layer comprises one of a Group III-V semiconductor, a Group II-VI semiconductor, a Group III-V semiconductor alloy, and a Group II-VI semiconductor alloy.

49. The electronic device of claim 40 wherein the electronic device is a multiple junction solar cell comprising:

a substrate having a hexagonal crystal system structure; and

a crystalline semiconductor layer having a cubic crystalline structure.

50. The electronic device of claim 49 wherein the substrate comprises a hexagonal crystal family material and the crystalline semiconductor layer comprises one of a Group IV semiconductor, a Group III-V semiconductor, a Group II-VI semiconductor, a Group IV semiconductor alloy, a Group III-V semiconductor alloy, and a Group II-VI semiconductor alloy.

51. The electronic device of claim 40 wherein the device is a multiple junction solar cell comprising:

a substrate having a hexagonal crystal system structure; and

a crystalline semiconductor layer having a hexagonal crystalline structure.

52. The electronic device of claim 51 wherein the substrate comprises a hexagonal crystal family material and the crystalline semiconductor layer comprises one of a Group III-V semiconductor, a Group II-VI semiconductor, a Group III-V semiconductor alloy, and a Group II-VI semiconductor alloy.