SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

• US 20110147805A1
• Filed: 02/28/2011
• Published: 06/23/2011
• Est. Priority Date: 12/08/2006
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Takagi, Shinichi, Sugiyama, Naoharu, Irisawa, Toshifumi
• Granted Patent: US 8,174,095 B2
• Time in Patent Office: Days
• US Class Current: 257/255
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78684 having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence

Abstract

A semiconductor device includes an insulator layer, and an n-channel MIS transistor having an n channel and a pMIS transistor having a p channel which are formed on the insulator layer, wherein the n channel of the n-channel MIS transistor is formed of an Si layer having a uniaxial tensile strain in a channel length direction, the p channel of the p-channel MIS transistor is formed of an SiGe or Ge layer having a uniaxial compressive strain in the channel length direction, and the channel length direction of each of the n-channel MIS transistor and the p-channel MIS transistor is a <110> direction.

Claims

1. A semiconductor device comprising:

an insulator layer;

a first semiconductor region formed in a linear shape having two side surfaces along one direction on the insulator layer, having a <

110>

direction as a longitudinal direction thereof, and being made of Si having a uniaxial tensile strain in the <

110>

direction;

an n-channel MIS transistor formed in the first semiconductor region, the n-channel MIS transistor including a first gate electrode formed on at least the two side surfaces of the first semiconductor region through a first gate insulating film and having the <

110>

direction as a channel length direction thereof and a first source/drain region formed on the first semiconductor region to interpose the first gate electrode therebetween;

a second semiconductor region formed in a linear shape having two side surfaces on the insulator layer in parallel with the first semiconductor region, having the <

110>

direction as a longitudinal direction thereof, and being made of SiGe or Ge having a uniaxial compressive strain in the <

110>

direction; and

a p-channel MIS transistor formed on the second semiconductor region, the p-channel MIS transistor including a second gate electrode formed on at least the two side surfaces of the second semiconductor region through a second gate insulating film and having the <

110>

direction as a channel length direction thereof and a second source/drain region formed on the second semiconductor region to interpose the first gate electrode therebetween,

wherein each of the first gate electrode and the second gate electrode is formed on the two side surfaces as well as upper and lower surfaces of each of the first semiconductor region and the second semiconductor region.

2. The device according to claim 1, wherein the upper surface of each of the first semiconductor region and the second semiconductor region is a (001) surface.

3. The device according to claim 1, wherein the upper surface of each of the first semiconductor region and the second semiconductor region is a (110) surface.

4. The device according to claim 1, wherein a width of each of the first semiconductor region and the second semiconductor region perpendicular to the longitudinal direction thereof falls within the range of 5 nm to 500 nm, each limit inclusive.

5. The device according to claim 1, wherein the two side surfaces of each of the first semiconductor region and the second semiconductor region are (110) surfaces.

6. The device according to claim 1, wherein a strain amount of each of the unixaial tensile strain and the uniaxial compressive strain is 0.4% or above.

7. The device according to claim 1, wherein a strain amount of each of the unixaial tensile strain and the uniaxial compressive strain is 0.8% or above.