ASYMMETRIC JUNCTION FIELD EFFECT TRANSISTOR
First Claim
1. A semiconductor structure comprising:
- a body layer comprising a semiconductor material and having a doping of a first conductivity type and located in a semiconductor substrate;
a source region comprising said semiconductor material and having a doping of said first conductivity type and laterally abutting said body layer;
a drain region comprising said semiconductor material and having a doping of said first conductivity type and laterally abutting said body layer;
an upper gate region comprising said semiconductor material and having a doping of a second conductivity type and vertically abutting a top surface of said body layer, wherein said second conductivity type is the opposite of said first conductivity type; and
a lower gate region comprising said semiconductor material and having a doping of said second conductivity type and vertically abutting a bottom surface of said body layer and laterally abutting sidewalls of said body layer and abutting said upper gate region, wherein said source region and said drain region have substantially coplanar top surfaces, and wherein a bottom surface of said source region is located below a level of a bottommost surface of said drain region.
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Abstract
A junction field effect transistor (JFET) in a semiconductor substrate includes a source region, a drain region, a channel region, an upper gate region, and a lower gate region. The lower gate region is electrically connected to the upper gate region. The upper and lower gate regions control the current flow through the channel region. By performing an ion implantation step that extends the thickness of the source region to a depth greater than the thickness of the drain region, an asymmetric JFET is formed. The extension of depth of the source region relative to the depth of the drain region reduces the length for minority charge carriers to travel through the channel region, reduces the on-resistance of the JFET, and increases the on-current of the JFET, thereby enhancing the overall performance of the JFET without decreasing the allowable Vds or dramatically increasing Voff/Vpinch.
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Citations
15 Claims
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1. A semiconductor structure comprising:
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a body layer comprising a semiconductor material and having a doping of a first conductivity type and located in a semiconductor substrate; a source region comprising said semiconductor material and having a doping of said first conductivity type and laterally abutting said body layer; a drain region comprising said semiconductor material and having a doping of said first conductivity type and laterally abutting said body layer; an upper gate region comprising said semiconductor material and having a doping of a second conductivity type and vertically abutting a top surface of said body layer, wherein said second conductivity type is the opposite of said first conductivity type; and a lower gate region comprising said semiconductor material and having a doping of said second conductivity type and vertically abutting a bottom surface of said body layer and laterally abutting sidewalls of said body layer and abutting said upper gate region, wherein said source region and said drain region have substantially coplanar top surfaces, and wherein a bottom surface of said source region is located below a level of a bottommost surface of said drain region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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Specification