POLISH TO REMOVE TOPOGRAPHY IN SACRIFICIAL GATE LAYER PRIOR TO GATE PATTERNING

• US 20110147812A1
• Filed: 12/23/2009
• Published: 06/23/2011
• Est. Priority Date: 12/23/2009
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Morimoto, Seiichi, Zelick, Nancy, Steigerwald, Joseph M., Shah, Uday
• Granted Patent: US 8,334,184 B2
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: H01L 21/28123 Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Techniques are disclosed for fabricating FinFET transistors (e.g., double-gate, trigate, etc). A sacrificial gate material (such as polysilicon or other suitable material) is deposited on fin structure, and polished to remove topography in the sacrificial gate material layer prior to gate patterning. A flat, topography-free surface (e.g., flatness of 50 nm or better, depending on size of minimum feature being formed) enables subsequent gate patterning and sacrificial gate material opening (via polishing) in a FinFET process flow. Use of the techniques described herein may manifest in structural ways. For instance, a top gate surface is relatively flat (e.g., flatness of 5 to 50 nm, depending on minimum gate height or other minimum feature size) as the gate travels over the fin. Also, a top down inspection of gate lines will generally show no or minimal line edge deviation or perturbation as the line runs over a fin.

Claims

1. A method for fabricating a semiconductor transistor, comprising:

forming a fin structure on a substrate;

depositing sacrificial gate material over the fin structure; and

polishing the sacrificial gate material, prior to gate patterning of the sacrificial gate material and transistor formation.

2. The method of claim 1 further comprising:

from a single depth of focus, patterning the sacrificial gate material in preparation for forming gate, source, and drain regions of the transistor.

3. The method of claim 2 further comprising:

forming the gate, source, and drain regions.

4. The method of claim 3 further comprising at least one of:

depositing an etch stop layer over the gate region; and

depositing a dielectric layer over the gate, source, and drain regions.

5. The method of claim 4 further comprising:

planarizing the dielectric layer to open the sacrificial gate material.

6. The method of claim 5 further comprising:

removing the sacrificial gate material from the gate region, thereby forming a gate trench.

7. The method of claim 6 further comprising at least one of:

depositing gate metal into the gate trench; and

polishing to remove any excess metal.

8. The method of claim 1 wherein a plurality of fin structures and transistors are formed on the substrate.

9. The method of claim 1 wherein the substrate comprises silicon and the sacrificial gate material comprises polysilicon.

10. The method of claim 1 wherein the transistor is a FinFET device.

11. A semiconductor transistor device, comprising:

a fin structure formed on a substrate; and

a plane established pre-gate-patterning by a polished sacrificial gate material deposited over the fin structure, the plane defining a single depth of focus used for gate patterning of the sacrificial gate material to provide gate, source and drain regions.

12. The device of claim 11 further comprising:

a dielectric layer deposited over the gate, source, and drain regions, the dielectric layer having been planarized to open the sacrificial gate material.

13. The device of claim 12 wherein the sacrificial gate material is removed from the gate region to provide a gate trench, the device further comprising gate metal deposited into the gate trench, wherein the gate metal is polished to remove any excess metal.

14. The device of claim 11 wherein the polished sacrificial gate material is polished to a flatness is 1 nm to 10 nm.

15. The device of claim 11 wherein a plurality of fin structures and transistors are formed on the substrate.

16. The device of claim 11 further comprising dielectric material deposited in trenches neighboring the fin structure, the dielectric material having a top surface that is recessed below a top surface of the fin structure.

17. The device of claim 11 wherein the transistor is a FinFET device.

18. The device of claim 11 wherein the polished sacrificial gate material is polished to a flatness is 1 nm to 5 nm.

19. A method for fabricating semiconductor transistors, comprising:

forming a plurality of fin structures on a substrate;

depositing sacrificial gate material over the fin structures;

polishing the sacrificial gate material, prior to gate patterning of the sacrificial gate material and transistor formation, so that the sacrificial gate material has a flatness of 10 nm or better;

from a single depth of focus, patterning the sacrificial gate material in preparation for forming gate, source, and drain regions of the transistors;

forming the gate, source, and drain regions;

depositing a dielectric layer over the gate, source, and drain regions;

planarizing the dielectric layer to open the sacrificial gate material;

removing the sacrificial gate material from the gate regions, thereby forming gate trenches; and

depositing gate metal into the gate trenches.

20. The method of claim 19 wherein the transistor is a FinFET device.