SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREOF

• US 20110147815A1
• Filed: 12/20/2010
• Published: 06/23/2011
• Est. Priority Date: 12/21/2009
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: TAKEDA, Hiroshi
• Granted Patent: US 8,502,319 B2
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/41725 Source or drain electrodes for field effect devices with monocrystalline semiconductor on source/drain region H01L29/0843
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Disclosed is a semiconductor device wherein device characteristics are improved by applying a strong stress to a channel region. The semiconductor device includes a semiconductor substrate, a gate insulating film formed over a first plane of the semiconductor substrate, a gate electrode formed over the gate insulating film, a gate sidewall insulating film formed over the sidewall of the gate electrode, source/drain diffusion layer regions into which impurities are implanted, the source/drain diffusion layer regions being adjacent to a channel region formed in the semiconductor substrate below the gate electrode, and a stress applying film formed over the source/drain diffusion layer regions except over the upper part of the gate electrode; and recesses or protrusions are formed in the region where the source/drain diffusion layer regions are formed over the first plane of the semiconductor substrate.

Claims

1. A semiconductor device comprising:

a semiconductor substrate;

a gate insulating film formed over a first plane of the semiconductor substrate;

a gate electrode formed over the gate insulating film;

a gate sidewall insulating film formed over the sidewall of the gate electrode;

a source/drain diffusion layer region, being adjacent to a channel region formed in the semiconductor substrate below the gate electrode, into which impurities are implanted; and

a stress applying film formed over the source/drain diffusion layer region except over the upper part of the gate electrode,

wherein a recess or a protrusion is formed in the region where the source/drain diffusion layer region is formed over the first plane of the semiconductor substrate.

2. The semiconductor device according to claim 1,

wherein the protrusion is formed by protruding the source/drain diffusion layer region from the first plane of the semiconductor substrate.

3. The semiconductor device according to claim 1,

wherein at least a part of the recess or the protrusion extends in the direction intersecting with a first straight line intersecting nearly perpendicularly with the direction where the gate electrode extends.

4. The semiconductor device according to claim 3,

wherein at least a part of the recess or the protrusion extends in the direction intersecting nearly perpendicularly with the first straight line.

5. The semiconductor device according to claim 3,

wherein a plurality of the recesses or the protrusions are formed and at least some of the plural recesses or protrusions are aligned nearly parallel with each other.

6. The semiconductor device according to claim 1,

wherein the stress applying film comprises a contractive material.

7. The semiconductor device according to claim 1,

wherein the stress applying film comprises an expansive material.

8. The semiconductor device according to claim 1,

wherein the semiconductor substrate includes a first semiconductor layer, an insulating film layer formed over the surface of the first semiconductor layer, and a second semiconductor layer formed over the insulating film layer, and

wherein the plane opposite to the plane of the second semiconductor layer touching the insulating film layer constitutes the first plane of the semiconductor substrate.

9. The semiconductor device according to claim 1,

wherein an interstice is formed between the gate sidewall insulating film and the protrusion in the source/drain diffusion layer region, and

wherein the stress applying film is formed in the interstice.

10. The semiconductor device according to claim 8,

wherein the first plane of the semiconductor substrate has a convex shape;

and

wherein the gate insulating film is formed continuously over the upper plane and the side plane of the convex shape.

11. A method for producing a semiconductor device, comprising the steps of:

forming a gate insulating film over a first plane of a semiconductor substrate and a gate electrode over the gate insulating film;

forming a first layer over a first region that is a region in the semiconductor substrate adjacent to a region where the gate insulating film and the gate electrode are formed, at least a part of the plane of the first layer opposite to the plane touching the first region being not nearly parallel with the first plane of the semiconductor substrate;

implanting impurities into the first layer and forming a source/drain diffusion layer region; and

forming a stress applying film over the source/drain diffusion layer region except over the upper part of the gate electrode,

wherein the first layer includes a material having a stronger adhesiveness with the semiconductor substrate than the stress applying film has.

12. The method for producing a semiconductor device according to claim 11,

wherein the first plane of the semiconductor substrate comprises a first semiconductor, and

wherein the process of forming the first layer is a process of forming the first layer by growing the first semiconductor by a CVD method.

13. The method for producing a semiconductor device according to claim 11,

wherein the first plane of the semiconductor substrate includes a first semiconductor, and wherein the step of forming the first layer further

includes the steps of:

selectively digging down the first region by photolithography and etching; and

forming the first layer filling also the dug down region by growing the first semiconductor or a semiconductor other than the first semiconductor by a CVD method.

14. The method for producing a semiconductor device according to claim 12, wherein the process of forming the first layer further includes a process of forming convexes and concaves over a layer by photolithography and etching after the layer is formed by growing the first semiconductor or the semiconductor other than the first semiconductor.

15. The method for producing a semiconductor device according to claim 11,

wherein the semiconductor substrate includes a first semiconductor layer, an insulating film layer formed over the surface of the first semiconductor layer, and a second semiconductor layer formed over the surface of the insulating film layer;

and

wherein the plane opposite to the plane of the second semiconductor layer touching the insulating film layer constitutes the first plane of the semiconductor substrate.