SPIN TORQUE MAGNETIC INTEGRATED CIRCUITS AND DEVICES THEREFOR

• US 20110147816A1
• Filed: 12/18/2009
• Published: 06/23/2011
• Est. Priority Date: 12/18/2009
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Ghani, Tahir, Bourianoff, George I., Nikonov, Dmitri E.
• Granted Patent: US 8,063,460 B2
• Time in Patent Office: Days
• US Class Current: 257/295
• CPC Class Codes: B82Y 25/00 Nanomagnetism, e.g. magnetoimpedance, anisotropic magnetoresistance, giant magnetoresistance or tunneling magnetoresistance
• CPC Class Codes: B82Y 40/00 Manufacture or treatment of nanostructures
• CPC Class Codes: G01R 33/093 using multilayer structures, e.g. giant magnetoresistance sensors thin magnetic films H01F10/00
• CPC Class Codes: G01R 33/1284 Spin resolved measurements; Influencing spins during measurements, e.g. in spintronics devices G01R33/093 takes precedence; semiconductor devices using spin polarized carriers H01L29/66984
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: H01F 10/133 containing rare earth metals
• CPC Class Codes: H01F 10/3254 the spacer being semiconducting or insulating, e.g. for spin tunnel junction [STJ]
• CPC Class Codes: H01F 10/329 Spin-exchange coupled multilayers wherein the magnetisation of the free layer is switched by a spin-polarised current, e.g. spin torque effect
• CPC Class Codes: H01F 41/307 insulating or semiconductive spacer
• CPC Class Codes: H10B 61/00 Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type
• CPC Class Codes: H10N 50/01 Manufacture or treatment
• CPC Class Codes: H10N 50/10 Magnetoresistive devices
• CPC Class Codes: H10N 59/00 Integrated devices, or assemblies of multiple devices, comprising at least one galvanomagnetic or Hall-effect element covered by groups H10N50/00 - H10N52/00 MRAM devices H10B61/00

Abstract

Spin torque magnetic integrated circuits and devices therefor are described. A spin torque magnetic integrated circuit includes a first free ferromagnetic layer disposed above a substrate. A non-magnetic layer is disposed above the first free ferromagnetic layer. A plurality of write pillars and a plurality of read pillars are included, each pillar disposed above the non-magnetic layer and including a fixed ferromagnetic layer.

Claims

1. A spin torque magnetic integrated circuit, comprising:

a first free ferromagnetic layer disposed above a substrate;

a non-magnetic layer disposed above the first free ferromagnetic layer; and

a plurality of write pillars and a plurality of read pillars, each pillar disposed above the non-magnetic layer and comprising a fixed ferromagnetic layer.

2. The spin torque magnetic integrated circuit of claim 1, wherein the non-magnetic layer is a tunnel oxide layer, the spin torque magnetic integrated circuit further comprising:

a coupling layer disposed on the first free ferromagnetic layer;

a second free ferromagnetic layer disposed on the coupling layer, wherein the non-magnetic layer is disposed above the second free ferromagnetic layer; and

an anti-ferromagnetic layer disposed above the fixed ferromagnetic layer.

3. The spin torque magnetic integrated circuit of claim 2, wherein the coupling layer is for stabilizing an alignment of magnetization in the first and second free ferromagnetic layers.

4. The spin torque magnetic integrated circuit of claim 3, wherein the coupling layer comprises ruthenium (Ru) and the first and second free ferromagnetic layers comprise terbium cobalt iron (TbCoFe).

5. The spin torque magnetic integrated circuit of claim 4, wherein the tunnel oxide layer is disposed directly on the second free ferromagnetic layer and comprises magnesium oxide (MgO) or aluminum oxide (Al₂O₃), and wherein each of the plurality of write pillars and each of the plurality of read pillars comprises a copper layer disposed on the anti-ferromagnetic layer, and comprises an intervening layer disposed directly between the anti-ferromagnetic layer and the fixed ferromagnetic layer, the fixed ferromagnetic layer disposed directly on the tunnel oxide layer.

6. The spin torque magnetic integrated circuit of claim 2, wherein the coupling layer has a thickness of less than approximately 1 nanometer.

7. A spin torque magnetic integrated circuit, comprising:

a first free ferromagnetic layer disposed on a portion of a substrate, the first free ferromagnetic layer comprising a sidewall;

a first coupling layer disposed on the first free ferromagnetic layer, the first coupling layer conformal with the sidewall and adjacent to an exposed portion of the substrate;

a second free ferromagnetic layer disposed on the first coupling layer and on the exposed portion of the substrate, the second free ferromagnetic coupling layer conformal with the first coupling layer;

a second coupling layer disposed on the second free ferromagnetic layer, the upper-most surface of the second coupling layer approximately planar with the upper-most surface of the second free ferromagnetic layer;

a third free ferromagnetic layer disposed on the portion of the second coupling layer above the exposed portion of the substrate, the upper-most surface of the third free ferromagnetic layer approximately planar with the upper-most surface of the second coupling layer;

a non-magnetic layer disposed on the upper-most surfaces of the second coupling layer and the second and third free ferromagnetic layers; and

a write pillar and a read pillar, each pillar disposed above the non-magnetic layer and comprising a fixed ferromagnetic layer.

8. The spin torque magnetic integrated circuit of claim 7, wherein the non-magnetic layer is a tunnel oxide layer, the spin torque magnetic integrated circuit further comprising:

an anti-ferromagnetic layer disposed above the fixed ferromagnetic layer.

9. The spin torque magnetic integrated circuit of claim 8, wherein the first, second and third free ferromagnetic layers form an inverter.

10. The spin torque magnetic integrated circuit of claim 8, wherein the first coupling layer is for stabilizing an alignment of magnetization in the first and second free ferromagnetic layers.

11. The spin torque magnetic integrated circuit of claim 10, wherein the first coupling layer comprises ruthenium (Ru) and the first and second free ferromagnetic layers comprise terbium cobalt iron (TbCoFe).

12. The spin torque magnetic integrated circuit of claim 11, wherein the tunnel oxide layer is disposed directly on the upper-most surfaces of the second coupling layer and the second and third free ferromagnetic layers and comprises magnesium oxide (MgO) or aluminum oxide (Al₂O₃), and wherein each of the write pillar and the read pillar comprises a copper layer disposed on the anti-ferromagnetic layer, and comprises an intervening layer disposed directly between the anti-ferromagnetic layer and the fixed ferromagnetic layer, the fixed ferromagnetic layer disposed directly on the tunnel oxide layer.

13. The spin torque magnetic integrated circuit of claim 8, wherein the second coupling layer is for stabilizing an alignment of magnetization in the second and third free ferromagnetic layers.

14. The spin torque magnetic integrated circuit of claim 13, wherein the second coupling layer comprises ruthenium (Ru) and the second and third free ferromagnetic layers comprise terbium cobalt iron (TbCoFe).

15. The spin torque magnetic integrated circuit of claim 14, wherein the tunnel oxide layer is disposed directly on the upper-most surfaces of the second coupling layer and the second and third free ferromagnetic layers and comprises magnesium oxide (MgO) or aluminum oxide (Al₂O₃), and wherein each of the write pillar and the read pillar comprises a copper layer disposed on the anti-ferromagnetic layer, and comprises an intervening layer disposed directly between the anti-ferromagnetic layer and the fixed ferromagnetic layer, the fixed ferromagnetic layer disposed directly on the tunnel oxide layer.

16. The spin torque magnetic integrated circuit of claim 8, wherein the substrate comprises a top dielectric layer disposed on a metal layer.

17. The spin torque magnetic integrated circuit of claim 8, wherein the portion of the first coupling layer between the first and second free ferromagnetic layers has a thickness of less than approximately 1 nanometer, and wherein the portion of the second coupling layer between the second and third free ferromagnetic layers has a thickness of less than approximately 1 nanometer.

18. A method of fabricating a spin torque magnetic integrated circuit, the method comprising:

forming a first free ferromagnetic layer on a portion of a substrate, the first free ferromagnetic layer comprising a sidewall;

forming a first coupling layer on the first free ferromagnetic layer, the first coupling layer conformal with the sidewall and adjacent to an exposed portion of the substrate;

forming a second free ferromagnetic layer on the first coupling layer and on the exposed portion of the substrate, the second free ferromagnetic coupling layer conformal with the first coupling layer;

forming a second coupling layer on the second free ferromagnetic layer, the upper-most surface of the second coupling layer approximately planar with the upper-most surface of the second free ferromagnetic layer;

forming a third free ferromagnetic layer on the portion of the second coupling layer above the exposed portion of the substrate, the upper-most surface of the third free ferromagnetic layer approximately planar with the upper-most surface of the second coupling layer;

forming a non-magnetic layer on the upper-most surfaces of the second coupling layer and the second and third free ferromagnetic layers; and

forming a write pillar and a read pillar, each pillar formed above the non-magnetic layer and comprising an anti-ferromagnetic layer formed above a fixed ferromagnetic layer.

19. The method of claim 18, wherein forming the non-magnetic layer comprises forming a tunnel oxide layer, the method further comprising:

forming an anti-ferromagnetic layer disposed above the fixed ferromagnetic layer.

20. The method of claim 19, wherein forming the first, second and third free ferromagnetic layers forms an inverter.

21. The method of claim 19, wherein forming the first free ferromagnetic layer on the portion of the substrate comprises forming the first free ferromagnetic layer on a dielectric layer disposed on a metal layer.

22. The method of claim 21, wherein the tunnel oxide layer is formed directly on the upper-most surfaces of the second coupling layer and the second and third free ferromagnetic layers and comprises magnesium oxide (MgO) or aluminum oxide (Al₂O₃), and wherein each of the write pillar and the read pillar comprises a copper layer formed on the anti-ferromagnetic layer, and comprises an intervening layer formed directly between the anti-ferromagnetic layer and the fixed ferromagnetic layer, the fixed ferromagnetic layer formed directly on the tunnel oxide layer.

23. The method of claim 19, wherein the portion of the first coupling layer between the first and second free ferromagnetic layers has a thickness of less than approximately 1 nanometer, and wherein the portion of the second coupling layer between the second and third free ferromagnetic layers has a thickness of less than approximately 1 nanometer.