SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATING THE SAME

• US 20110147824A1
• Filed: 12/15/2010
• Published: 06/23/2011
• Est. Priority Date: 12/16/2009
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Son, Yong-Hoon, Hwang, Kihun, Jeong, Jaehun, Baik, Seungjae
• Granted Patent: US 8,482,049 B2
• Time in Patent Office: Days
• US Class Current: 257/324
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

In semiconductor devices and methods of manufacture, a semiconductor device comprises a substrate of semiconductor material extending in a horizontal direction. A plurality of interlayer dielectric layers are on the substrate. A plurality of gate patterns are provided, each gate pattern between a neighboring lower interlayer dielectric layer and a neighboring upper interlayer dielectric layer. A vertical channel of semiconductor material is on the substrate and extending in a vertical direction through the plurality of interlayer dielectric layers and the plurality of gate patterns. The vertical channel has an outer sidewall, the outer sidewall having a plurality of channel recesses, each channel recess corresponding to a gate pattern of the plurality of gate patterns. The vertical channel has an inner sidewall. An information storage layer is present in the recess between each gate pattern and the vertical channel that insulates the gate pattern from the vertical channel.

Claims

1. A semiconductor device comprising:

a substrate of semiconductor material extending in a horizontal direction;

a plurality of interlayer dielectric layers on the substrate;

a plurality of gate patterns, each gate pattern between a neighboring lower interlayer dielectric layer and a neighboring upper interlayer dielectric layer;

a vertical channel of semiconductor material on the substrate and extending in a vertical direction through the plurality of interlayer dielectric layers and the plurality of gate patterns, the vertical channel having an outer sidewall, the outer sidewall having a plurality of channel recesses, each channel recess corresponding to a gate pattern of the plurality of gate patterns, the vertical channel having an inner sidewall; and

an information storage layer in the recess between each gate pattern and the vertical channel that insulates the gate pattern from the vertical channel.

2. The semiconductor device of claim 1 wherein the vertical channel has a cup shape and further comprising a vertical channel insulator that fills a vertical cavity in the vertical channel.

3. The semiconductor device of claim 1 wherein the vertical channel comprises first and second opposed plates that are spaced apart from each other and further comprising a vertical channel insulator between the first and second opposed plates.

4. The semiconductor device of claim 1 further comprising an etch stop layer positioned between a lowermost gate pattern of the plurality of gate patterns and the substrate.

5. The semiconductor device of claim 1 wherein a lowermost gate pattern of the plurality of gate patterns is positioned in a substrate recess in a top surface of the substrate.

6. The semiconductor device of claim 1 wherein each channel recess has a rounded concave surface that is opposite a corresponding one of the gate patterns having a mating rounded convex surface, and wherein the rounded convex surface of each gate pattern is positioned in a rounded concave surface of a corresponding channel recess.

7. The semiconductor device of claim 6 wherein the mating rounded convex surface of the gate pattern positioned in the channel recess has a width in the vertical direction that is greater than a thickness of a body portion of the gate pattern positioned between the neighboring lower interlayer dielectric layer and the neighboring upper interlayer dielectric layer of the gate pattern.

8. The semiconductor device of claim 6 wherein the mating rounded convex surface of the gate pattern positioned in the channel recess has a width in the vertical direction that is less than a thickness of a body portion of the gate pattern positioned between the neighboring lower interlayer dielectric layer and the neighboring upper interlayer dielectric layer of the gate pattern.

9. The semiconductor device of claim 1 wherein a first distance between the outer sidewall and the inner sidewall of a first portion of the vertical channel adjacent the channel recess in a horizontal direction is less than a second distance between the outer sidewall and an inner sidewall of a second portion of the vertical channel adjacent the interlayer dielectric layer in the horizontal direction

10. The semiconductor device of claim 1 wherein the information storage layer further extends in a horizontal direction between the gate pattern and the neighboring upper interlayer dielectric layer;

and extends in the horizontal direction between the gate pattern and the neighboring lower interlayer dielectric layer.

11. The semiconductor device of claim 1 wherein:

an upper-most gate pattern of the plurality of gate patterns comprises an upper select gate of an upper select transistor;

a lower-most gate pattern of the plurality of gate patterns comprises a lower select gate of a lower select transistor;

remaining gate patterns of the plurality of gate patterns between the upper select gate and the lower select gate comprise control gates of memory cell transistors of a common string of the semiconductor device;

control gates of memory cell transistors sharing a same layer of the device arranged in a first horizontal direction of the semiconductor device are connected to provide word lines of the semiconductor device;

memory cell transistors of a common string of the semiconductor device are coupled together in series by the vertical channel;

upper portions of vertical channels arranged in a second horizontal direction of the semiconductor device are connected to provide bit lines of the semiconductor device; and

the semiconductor device comprises a semiconductor memory device.

12. The semiconductor device of claim 1, wherein the inner sidewall is linear in extension in the vertical direction.

13. A semiconductor device comprising:

a substrate of semiconductor material extending in a horizontal direction;

a plurality of interlayer dielectric layers on the substrate;

a plurality of gate patterns, each gate pattern between a neighboring lower interlayer dielectric layer and a neighboring upper interlayer dielectric layer;

a vertical channel of semiconductor material on the substrate and extending in a vertical direction through the plurality of interlayer dielectric layers and the plurality of gate patterns, the vertical channel having an outer sidewall, the outer sidewall having a plurality of channel recesses, each channel recess corresponding to a gate pattern of the plurality of gate patterns, a lowermost gate pattern of the plurality of gate patterns being positioned in a substrate recess in a top surface of the substrate; and

an information storage layer in the channel recess between each gate pattern and the vertical channel that insulates the gate pattern from the vertical channel.

14. The semiconductor device of claim 13, wherein the vertical channel further has an inner sidewall, the inner sidewall being linear in extension in the vertical direction.

15. The semiconductor device of claim 13, wherein the vertical channel has a cup shape and further comprising a vertical channel insulator that fills a vertical cavity in the vertical channel.

16. The semiconductor device of claim 13, wherein the vertical channel is solid between the outer sidewalls.

17. The semiconductor device of claim 13, wherein the vertical channel comprises first and second opposed plates that are spaced apart from each other and further comprising a vertical channel insulator between the first and second opposed plates.

18. The semiconductor device of claim 13, further comprising an etch stop layer positioned between a lowermost gate pattern of the plurality of gate patterns and the substrate.

19. The semiconductor device of claim 13, wherein each channel recess has a rounded concave surface that is opposite a corresponding one of the gate patterns having a mating rounded convex surface, and wherein the rounded convex surface of each gate pattern is positioned in a rounded concave surface of a corresponding channel recess.

20. The semiconductor device of claim 19, wherein the mating rounded convex surface of the gate pattern positioned in the channel recess has a width in the vertical direction that is greater than a thickness of a body portion of the gate pattern positioned between the neighboring lower interlayer dielectric layer and the neighboring upper interlayer dielectric layer of the gate pattern.

21. The semiconductor device of claim 19, wherein the mating rounded convex surface of the gate pattern positioned in the channel recess has a width in the vertical direction that is less than a thickness of a body portion of the gate pattern positioned between the neighboring lower interlayer dielectric layer and the neighboring upper interlayer dielectric layer of the gate pattern.

22. The semiconductor device of claim 19, wherein the vertical channel further has an inner sidewall and wherein a first distance between the outer sidewall and the inner sidewall of a first portion of the vertical channel adjacent the channel recess in a horizontal direction is less than a second distance between the outer sidewall and an inner sidewall of a second portion of the vertical channel adjacent the interlayer dielectric layer in the horizontal direction

23. The semiconductor device of claim 13, wherein the information storage layer further extends in a horizontal direction between the gate pattern and the neighboring upper interlayer dielectric layer;

and extends in the horizontal direction between the gate pattern and the neighboring lower interlayer dielectric layer.

24. The semiconductor device of claim 13, wherein:

an upper-most gate pattern of the plurality of gate patterns comprises an upper select gate of an upper select transistor;

a lower-most gate pattern of the plurality of gate patterns comprises a lower select gate of a lower select transistor;

remaining gate patterns of the plurality of gate patterns between the upper select gate and the lower select gate comprise control gates of memory cell transistors of a common string of the semiconductor device;

control gates of memory cell transistors sharing a same layer of the device arranged in a first horizontal direction of the semiconductor device are connected to provide word lines of the semiconductor device;

memory cell transistors of a common string of the semiconductor device are coupled together in series by the vertical channel;

upper portions of vertical channels arranged in a second horizontal direction of the semiconductor device are connected to provide bit lines of the semiconductor device; and

the semiconductor device comprises a semiconductor memory device.

25-46. -46. (canceled)