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Charged balanced devices with shielded gate trench

  • US 20110147836A1
  • Filed: 02/17/2011
  • Published: 06/23/2011
  • Est. Priority Date: 08/20/2008
  • Status: Active Grant
First Claim
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1. A semiconductor power device comprising:

  • a semiconductor substrate including a plurality of deep trenches;

    an epitaxial layer filling said deep trenches, the epitaxial layer further including a simultaneously grown top epitaxial layer covering areas above a top surface of said deep trenches and over said semiconductor substrate, wherein the epitaxial layer is of an opposite conductivity type as the semiconductor substrate;

    a plurality of trench MOSFET cells disposed in said top epitaxial layer with the top epitaxial layer acting as the body region and the semiconductor substrate acting as the drain region whereby a super-junction effect is achieved through charge balance between the epitaxial layer in the deep trenches and regions in the semiconductor substrate laterally adjacent to the deep trenches; and

    each of said plurality of trench MOSFET cells further including a trench gate and a gate-shielding dopant region disposed below and substantially aligned with each of the trench gates for each of the trench MOSFET cells for shielding the trench gate during a voltage breakdown, wherein the gate-shielding dopant region has an opposite conductivity type as the substrate; and

    a gate-bottom dopant implant-region disposed below each of the trench gates implanted with a dopant having a same conductivity type as the substrate and are located above the gate-shielding dopant regions.

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