STACKABLE CIRCUIT STRUCTURES AND METHODS OF FABRICATION THEREOF

• US 20110147911A1
• Filed: 12/22/2009
• Published: 06/23/2011
• Est. Priority Date: 12/22/2009
• Status: Active Grant

• Current Assignee: EPIC Technologies Incorporated
• Original Assignee: EPIC Technologies Incorporated
• Inventors: Kohl, James E., Eichelberger, Charles W.
• Granted Patent: US 8,169,065 B2
• Time in Patent Office: Days
• US Class Current: 257/686
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/17181 On opposite sides of the body
• CPC Class Codes: H01L 2224/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 2224/2101 Structure
• CPC Class Codes: H01L 2224/2105 Shape
• CPC Class Codes: H01L 2224/211 Disposition
• CPC Class Codes: H01L 2224/221 Disposition
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06582 : Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 2225/1035 : the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/1082 : for improving alignment between containers, e.g. interlocking features
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01011 : Sodium [Na]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/07811 : Extrinsic, i.e. with electrical conductive fillers
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

Stackable circuit structures and methods of fabrication are provided employing first level metallization directly on a chips-first layer(s), which includes: a chip(s), each with a pad mask over its upper surface and openings exposing its contact pads; electrically conductive structures; and structural dielectric material surrounding the side surfaces of the chips and the conductive structures. Each chips-first layer further includes a metallization layer on the front surface of the layer, residing at least partially on the pad mask and extending over an edge of the chip. Together, the pad mask and the structural material electrically isolate the metallization layer from the chip. Input/output interconnect structures physically and electrically contact the metallization layer over the front surface and/or the lower surfaces of the electrically conductive structures at the back surface of the chips-first layer, to facilitate input/output connection to chips of the layers in a stack.

Claims

1. A circuit structure comprising:

at least one chips-first layer, each chips-first layer including;

at least one chip, each chip comprising at least one side surface, an upper surface, a lower surface, and at least one contact pad at the upper surface, and a pad mask over the upper surface with at least one opening therein exposing the at least one contact pad at the upper surface;

at least one electrically conductive structure comprising at least one side surface, an upper surface and a lower surface;

a structural material surrounding the at least one side surface of each chip of the at least one chip of the chips-first layer and surrounding the at least one side surface of each electrically conductive structure of the at least one electrically conductive structure, the structural material having an upper surface substantially coplanar with or parallel to at least one of the upper surface of the at least one chip or the upper surface of the at least one electrically conductive structure, and defining at least a portion of a front surface of the chips-first layer, and a lower surface substantially coplanar with or parallel to at least one of a lower surface of the at least one chip or a lower surface of the at least one electrically conductive structure, and defining at least a portion of a back surface of the chips-first layer, and wherein the structural material comprises a dielectric material;

a metallization layer at the front surface of the chips-first layer, the metallization layer residing at least partially on the upper surface of the structural material and at least partially on the pad mask of the at least one chip, and extending over at least one edge of the at least one chip, and wherein the metallization layer electrically connects the at least one contact pad on the upper surface of the at least one chip to the at least one electrically conductive structure, and the structural material and the pad mask over the upper surface of the at least one chip electrically isolate the metallization layer from the at least one edge of the at least one chip; and

at least one input/output interconnect structure disposed over the back surface of the at least one chips-first layer, the at least one input/output interconnect structure physically and electrically contacting the lower surface of at least one electrically conductive structure and facilitating electrical connection from the back surface of the at least one chips-first layer to the metallization layer at the front surface of the at least one chips-first layer.

2. The circuit structure of claim 1, wherein the structural material of a chips-first layer of the at least one chips-first layer extends to a height above the pad mask on a chip of that chips-first layer.

3. The circuit structure of claim 1, wherein the structural material of a chips-first layer of the at least one chips-first layer extends over a portion of the pad mask of the at least one chip at the at least one edge thereof, and wherein a majority of the pad mask of the at least one chip of the chips-first layer is exposed, being uncovered by the structural material.

4. The circuit structure of claim 1, wherein the at least one chip of a chips-first layer comprises multiple contact pads at the upper surface thereof, and wherein the metallization layer of that chips-first layer electrically connects to the multiple contact pads at the upper surface of the at least one chip.

5. The circuit structure of claim 4, wherein the metallization layer of the chips-first layer comprises a patterned metal interconnect that is narrower in width than a width of a contact pad of the multiple contact pads at the point of electrical connection thereto.

6. The circuit structure of claim 1, wherein the at least one electrically conductive structure of a chips-first layer of the at least one chips-first layer is fabricated at least partially of solder.

7. A circuit structure comprising:

a stack of multiple chips-first layers, each chips-first layer in the stack of multiple chips-first layers comprising;

at least one chip, each chip comprising at least one side surface, an upper surface, a lower surface, and at least one contact pad at the upper surface, and a pad mask over the upper surface with at least one opening therein exposing the at least one contact pad at the upper surface;

at least one electrically conductive structure comprising at least one side surface, an upper surface, and a lower surface;

a structural material surrounding the at least one side surface of each chip of the at least one chip of the chips-first layer and surrounding the at least one side surface of each electrically conductive structure of the at least one electrically conductive structure of the chips-first layer, the structural material having an upper surface substantially coplanar with or parallel to at least one of the upper surface of the at least one chip or the upper surface of the at least one electrically conductive structure, and defining at least a portion of a front surface of the chips-first layer, and a lower surface substantially coplanar with or parallel to at least one of the lower surface of the at least one chip or the lower surface of the at least one electrically conductive structure, and defining at least a portion of a back surface of the chips-first layer, wherein the structural material comprises a dielectric material;

a metallization layer residing at least partially on the upper surface of the structural material and at least partially on the pad mask of the at least one chip, and extending over at least one edge of the least one chip, and wherein the metallization layer electrically connects the at least one contact pad on the upper surface of the at least one chip to the at least one electrically conductive structure, and the structural material and the pad mask over the upper surface of the at least one chip electrically isolate the metallization layer from the at least one edge of the at least one chip; and

a plurality of input/output interconnect structures comprising input/output interconnect structures electrically connecting together a first chips-first layer and a second chips-first layer of the stack of multiple chips-first layers, the input/output interconnect structures being disposed between and electrically interconnecting at least one of the lower surface of an electrically conductive structure of the first chips-first layer and the metallization layer of the second chips-first layer, or the metallization layer of the first chips-first layer and the metallization layer of the second chips-first layer, or the lower surface of an electrically conductive structure of the first chips-first layer and the lower surface of an electrically conductive structure of the second chips-first layer.

8. The circuit structure of claim 7, wherein the plurality of input/output interconnect structures are fabricated of solder, and “

no clean flux”

or “

no flow flux”

.

9. The circuit structure of claim 7, wherein the plurality of input/output interconnect structures comprise at least one of a conductive polymer or an anisotropic conductive polymer.

10. The circuit structure of claim 7, wherein the input/output interconnect structures are disposed between and electrically connect together at least one of the lower surface of an electrically conductive structure of the first chips-first layer and the metallization layer of the second chips-first layer, or the lower surface of an electrically conductive structure of the first chips-first layer and the lower surface of an electrically conductive structure of the second chips-first layer, and wherein the at least one electrically conductive structure of the first chips-first layer comprises solder, and the input/output interconnect structures are fabricated of a material having a melting point higher than the solder of the at least one electrically conductive structure, and project at least partially into the electrically conductive structure of the first chips-first layer.

11. The circuit structure of claim 10, wherein the input/output interconnect structures comprise copper.

12. The circuit structure of claim 7, wherein the stack of multiple chips-first layers is electrically connected to electrical interconnect of a substrate layer.

13. The circuit structure of claim 12, wherein the plurality of input/output interconnect structures are a first plurality of input/output interconnect structures and wherein the substrate layer further comprises a second plurality of input/output interconnect structures, the second plurality of input/output interconnect structures having a different interconnect pitch than the first plurality of input/output interconnect structures.

14. The circuit structure of claim 12, wherein the multiple chips-first layers of the stack of multiple chips-first layers comprise memory chips, and wherein the substrate layer comprises at least one of a memory controller chip or a processor chip electrically connected to the stack of multiple memory chips.

15. The circuit structure of claim 7, wherein the plurality of input/output interconnect structures comprise a first plurality of input/output interconnect structures interconnecting at least two chips-first layers of the stack of multiple chips-first layers, and wherein the circuit structure further comprises a second plurality of input/output interconnect structures associated with the stack of multiple chips-first layers and providing electrical input/output connection to the stack of multiple chips-first layers.

16. The circuit structure of claim 7, further comprising an encapsulant material surrounding the multiple chips-first layers of the stack of multiple chips-first layers.

17. The circuit structure of claim 16, further comprising a stiffener layer physically coupled to the stack of multiple chips-first layers, the stiffener layer comprising a material different from the encapsulant material, and providing rigidity to the circuit structure.

18. A method of fabricating a circuit structure comprising:

forming a chips-first layer including;

obtaining at least one chip, each chip comprising at least one side surface, an upper surface, a lower surface, and at least one contact pad at the upper surface, and a pad mask over the upper surface with at least one opening therein exposing the at least one contact pad at the upper surface;

providing at least one electrically conductive structure comprising at least one side surface, an upper surface and a lower surface;

disposing structural material around the at least one side surface of each chip of the at least one chip of the at least one chips-first layer and surrounding the at least one side surface of each electrically conductive structure of the at least one electrically conductive structure, the structural material having an upper surface substantially coplanar with or parallel to at least one of the upper surface of the at least one chip or the upper surface of the at least one electrically conductive structure, and defining at least a portion of a front surface of the chips-first layer, and a lower surface substantially coplanar with or parallel to at least one of a lower surface of the at least one chip or a lower surface of the at least one electrically conductive structure, and defining at least a portion of a back surface of the chips-first layer, and wherein the structural material comprises a dielectric material; and

patterning a metallization layer on the front surface of the chips-first layer, the metallization layer residing at least partially on the upper surface of the structural material and at least partially on the pad mask of the at least one chip, and extending over at least one edge of the at least one chip, and wherein the metallization layer electrically connects the at least one contact pad on the upper surface of the at least one chip to the at least one electrically conductive structure, and the structural material and the pad mask over the upper surface of the at least one chip electrically isolate the metallization layer from the at least one edge of the at least one chip; and

providing at least one input/output interconnect structure disposed over the back surface of the at least one chips-first layer, the at least one input/output interconnect structure physically and electrically contacting the lower surface of the at least one electrically conductive structure and facilitating electrical connection from the back surface of the at least one chips-first layer to the metallization layer at the front surface of the at least one chips-first layer.

19. A method of fabricating a circuit structure comprising:

forming a stack of multiple chips-first layers, each chip s-first layer of the stack of multiple chips-first layers comprising;

at least one chip, each chip comprising at least one side surface, an upper surface, a lower surface, and at least one contact pad at the upper surface, and a pad mask over the upper surface with at least one opening therein exposing the at least one contact pad at the upper surface;

at least one electrically conductive structure comprising at least one side surface, an upper surface, and a lower surface;

a structural material surrounding the at least one side surface of each chip of the least one chip of the chips-first layer and surrounding the at least one side surface of each electrically conductive structure of the at least one electrically conductive structure of the chips-first layer, the structure material having an upper surface substantially coplanar with or parallel to at least one of the upper surface of the at least one chip or the upper surface of the at least one electrically conductive structure, and defining at least a portion of a front surface of the chips-first layer, and a lower surface substantially coplanar with or parallel to at least one of the lower surface of the at least one chip or the lower surface of the at least one electrically conductive structure, and defining at least a portion of a back surface of the chips-first layer, wherein the structural material comprises a dielectric material;

a metallization layer residing at least partially on the upper surface of the structural material and at least partially on the pad mask of the at least one chip, and extending over at least one edge of the least one chip, and wherein the metallization layer electrically connects the at least one contact pad on the upper surface of the at least one chip to the at least one electrically conductive structure, and the structural material and the pad mask over the upper surface of the at least one chip electrically isolate the metallization layer from the at least one edge of the at least one chip; and

providing a plurality of input/output interconnect structures comprising input/output interconnect structures electrically connecting together a first chips-first layer and a second chips-first layer of the stack of multiple chips-first layers, the input/output interconnect structures being disposed between and electrically interconnecting at least one of the lower surface of an electrically conductive structure of the first chips-first layer and the metallization layer of the second chips-first layer or the metallization layer of the first chips-first layer and the metallization layer of the second chips-first layer, or the lower surface of an electrically conductive structure of the first chips-first layer and the lower surface of an electrically conductive structure of the second chips-first layer.

20. A method of facilitating use of a process carrier during fabrication of a circuit structure, the method comprising:

during fabrication of the circuit structure, retaining a metal seed layer over a surface of the circuit structure disposed as a result of a metallization patterning of the surface of the circuit structure;

adhesively bonding the process carrier to the surface of the circuit structure;

subsequently separating the process carrier from the circuit structure, wherein at least a portion of adhesive securing the process carrier to the surface of circuit structure remains on the circuit structure;

etching the adhesive, wherein the seed metal protects the metallization patterning during etching of the adhesive; and

subsequently etching the seed metal from the surface of the circuit structure.