Post-Programming Functional Verification for Programable Integrated Circuits

• US 20110148462A1
• Filed: 10/20/2010
• Published: 06/23/2011
• Est. Priority Date: 10/20/2009
• Status: Active Grant

• Current Assignee: Siemens Industry Software Limited (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Landoll, David Scott
• Granted Patent: US 8,324,924 B2
• Time in Patent Office: Days
• US Class Current: 326/41
• CPC Class Codes: G06F 11/26 Functional testing
• CPC Class Codes: G06F 30/333 Design for testability [DFT], e.g. scan chain or built-in self-test [BIST]
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

Techniques and technology are provided to enable the testing of a programmable integrated circuit from within the programmable integrated circuit itself. In various implementations of the invention, a hardware verification module is added to the programmable integrated circuit by the manufacturer. Once the programmable integrated circuit is programmed to have a desired functionality, the hardware verification module may be activated and used to apply tests and receive responses from the programmable integrated circuit to verify its functionality.

Claims

1. A computer-implemented method for performing verification of an integrated circuit, the method comprising:

identifying an integrated circuit, the integrated circuit including a plurality of input/output pins and a verification component;

identifying a verification test, the verification test defining a signal and at least one of the plurality of input/output pins;

sending the verification test to the verification component;

causing the verification component to load the verification test onto the at least one of the plurality of input/output pins;

causing the integrated circuit to process at least one clock cycle;

causing the verification component to capture the states of the plurality of input/output pins;

receiving the states of the plurality of input output pins.

2. A computer-implemented method for performing verification of a programmable integrated circuit, the method comprising:

identifying a programmable integrated circuit, the programmable integrated circuit including a plurality of input/output pins and a verification component;

identifying a verification test;

sending the verification test to the verification component;

causing the verification component to load the verification test onto the at least one of the plurality of input/output pins;

causing the integrated circuit to process at least one clock cycle;

causing the verification component to capture the states of the plurality of input/output pins; and

receiving the states of the plurality of input/output pins from the verification component.

3. The computer-implemented method recited in claim 2, the verification test includes at least one verification test set, each at least one verification test set having:

one or more input signal names;

one or more input signal states corresponding to the one or more input signal names;

one or more output signal names;

one or more expected output signal states corresponding to the one or more output signal names; and

wherein the method act for causing the verification component to load the verification test onto the at least one of the plurality of input/output pins comprises;

identifying the one or more input/output pins that correspond to the one or more input signal names; and

applying the one or more input signal states to the one or more input/output pins corresponding to the one or more input signal names.

4. The computer-implemented method recited in claim 3, the method act for applying the one or more input signal states to the one or more input/output pins corresponding to the one or more input signal names comprising:

configuring the programmable integrated circuit such that electrical connection between the identified input/output pins and the verification component is made; and

applying a digital signal corresponding to the one or more input signal states onto the one or more identified input/output pins.

5. The computer-implemented method recited in claim 3, the method act for causing the verification component to capture the states of the plurality of input/output pins comprising:

identifying the one or more input/output pins that correspond to the one or more output signal names;

configuring the programmable integrated circuit such that electrical connection between the identified input/output pins and the verification component is made; and

identifying the state of one or more identified input/output pins after the programmable integrated circuit has processed the at least one clock cycle.

6. The computer-implemented method recited in claim 3, the verification test including a plurality of verification test sets, the method further comprising repeating the following method acts:

causing the verification component to load the verification test onto the at least one of the plurality of input/output pins;

causing the integrated circuit to process at least one clock cycle;

causing the verification component to capture the states of the plurality of input/output pins; and

wherein a different verification test set is loaded onto the at least one of the plurality of input/output pins during each repetition.

7. The computer-implemented method recited in claim 3, the method further comprising comparing the one or more expected output signal states to the states of the captured states.

8. The computer-implemented method recited in claim 2, further comprising causing the input/output pins to be electrically disconnected from signals external to the programmable integrated circuit.

9. One or more computer-readable media, having computer executable instructions for performing verification of a programmable integrated circuit stored thereon, the computer executable instructions comprising:

causing a computer to perform a set of operations; and

wherein the set of operations include;

identifying a programmable integrated circuit, the programmable integrated circuit including a plurality of input/output pins and a verification component;

identifying a verification test;

sending the verification test to the verification component;

causing the verification component to load the verification test onto the at least one of the plurality of input/output pins;

causing the integrated circuit to process at least one clock cycle;

causing the verification component to capture the states of the plurality of input/output pins; and

receiving the states of the plurality of input/output pins from the verification component.

10. The one or more computer-readable media recited in claim 9, the verification test includes at least one verification test set, each at least one verification test set having:

one or more input signal names;

one or more input signal states corresponding to the one or more input signal names;

one or more output signal names;

one or more expected output signal states corresponding to the one or more output signal names; and

wherein the operation for causing the verification component to load the verification test onto the at least one of the plurality of input/output pins comprises;

identifying the one or more input/output pins that correspond to the one or more input signal names; and

applying the one or more input signal states to the one or more input/output pins corresponding to the one or more input signal names.

11. The one or more computer-readable media recited in claim 10, the operation for applying the one or more input signal states to the one or more input/output pins corresponding to the one or more input signal names comprising:

configuring the programmable integrated circuit such that electrical connection between the identified input/output pins and the verification component is made; and

applying a digital signal corresponding to the one or more input signal states onto the one or more identified input/output pins.

12. The one or more computer-readable media recited in claim 10, the operation for causing the verification component to capture the states of the plurality of input/output pins comprising:

identifying the one or more input/output pins that correspond to the one or more output signal names;

configuring the programmable integrated circuit such that electrical connection between the identified input/output pins and the verification component is made; and

identifying the state of one or more identified input/output pins after the programmable integrated circuit has processed the at least one clock cycle.

13. The one or more computer-readable media recited in claim 10, the verification test including a plurality of verification test sets, the set of operations further comprising repeating the following operations:

causing the verification component to load the verification test onto the at least one of the plurality of input/output pins;

causing the integrated circuit to process at least one clock cycle;

causing the verification component to capture the states of the plurality of input/output pins; and

wherein a different verification test set is loaded onto the at least one of the plurality of input/output pins during each repetition.

14. The one or more computer-readable media recited in claim 10, the set of operations further comprising comparing the one or more expected output signal states to the captured states.

15. The one or more computer-readable media recited in claim 10, the set of operations further comprising:

causing the input/output pins to be electrically disconnected from signals external to the programmable integrated circuit.

16. An apparatus for verifying a programmable integrated circuit comprising:

an input/output port driver module configured to connect to a programmable integrated circuit, the programmable integrated circuit having a plurality of input/output pins and a verification component;

a test set generation module configured to receive a verification test set, the verification test set including;

one or more input signal names;

one or more input signal states corresponding to the one or more input signal names;

one or more output signal names; and

one or more expected output signal states corresponding to the one or more output signal names;

a test set mapping module configured to receive a pin mapping and then identify one or more of the input/output pins corresponding to a one of the signal names; and

a test set application module configured to;

send the verification test to the verification component;

causes the verification component to load the verification test onto the at least one of the plurality of input/output pins;

cause the integrated circuit to process at least one clock cycle;

cause the verification component to capture the states of the plurality of input/output pins; and

receive the captured states from the verification component.

17. The apparatus recited in claim 16, further comprising a result comparison module configured to compare the one or more expected output signal states to the captured states.

18. A programmable integrated circuit comprising:

a plurality of functional components;

a plurality if input/output pins;

a plurality of routing channels electrically connecting the plurality of input output pins to ones of the plurality of functional components and ones of the plurality of functional components to other ones of the plurality of functional components;

a plurality of switching components placed on the routing channels; and

a verification component.