NON-VOLATILE LATCH CIRCUIT AND LOGIC CIRCUIT, AND SEMICONDUCTOR DEVICE USING THE SAME

• US 20110148463A1
• Filed: 12/13/2010
• Published: 06/23/2011
• Est. Priority Date: 12/18/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kato, Kiyoshi, Koyama, Jun
• Granted Patent: US 8,314,637 B2
• Time in Patent Office: Days
• US Class Current: 326/47
• CPC Class Codes: G11C 14/0063 and the nonvolatile element is an EEPROM element, e.g. a floating gate or MNOS transistor
• CPC Class Codes: G11C 16/02 electrically programmable
• CPC Class Codes: H01L 21/8258 the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213 , H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H03K 19/1733 Controllable logic circuits H03K19/177 takes precedence
• CPC Class Codes: H03K 3/356008 ensuring a predetermined initial state when the supply voltage has been applied; storing the actual state when the supply voltage fails digital storage cells each combining volatile and non-volatile storage properties G11C14/00
• CPC Class Codes: H03K 3/35606 with synchronous operation
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

A novel non-volatile latch circuit and a semiconductor device using the non-volatile latch circuit are provided. The latch circuit has a loop structure in which an output of a first element is electrically connected to an input of a second element and an output of the second element is electrically connected to an input of the first element through a second transistor. A transistor using an oxide semiconductor as a semiconductor material of a channel formation region is used as a switching element, and a capacitor is provided to be electrically connected to a source electrode or a drain electrode of the transistor, whereby data of the latch circuit can be retained, and a non-volatile latch circuit can thus be formed.

Claims

1. A non-volatile latch circuit comprising:

a first transistor;

a second transistor;

a first element including a third transistor; and

a second element,

wherein an output of the first element is electrically connected to an input of the second element and an output of the second element is electrically connected to an input of the first element through the second transistor,

wherein the input of the first element is electrically connected to a wiring to which an input signal is applied through the first transistor and the output of the first element is electrically connected to a wiring to which an output signal is applied,

wherein one of a source electrode and a drain electrode of the first transistor is electrically connected to a gate of the third transistor, and the other of the source electrode and the drain electrode of the first transistor is electrically connected to the wiring to which the input signal is applied,

wherein one of a source electrode and a drain electrode of the second transistor is electrically connected to the gate of the third transistor, and the other of the source electrode and the drain electrode of the second transistor is electrically connected to the output of the second element, and

wherein a channel formation region of each of the first transistor and the second transistor includes an oxide semiconductor layer.

2. The non-volatile latch circuit according to claim 1, wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

3. The non-volatile latch circuit according to claim 1, wherein data stored in a gate capacitance of the third transistor is retained by the first transistor and the second transistor.

4. The non-volatile latch circuit according to claim 1,

wherein the first element is a first inverter and the second element is a second inverter.

5. The non-volatile latch circuit according to claim 1,

wherein the first element is a NAND and the second element is a clocked inverter.

6. The non-volatile latch circuit according to claim 1,

wherein at least one of the first transistor and the second transistor comprises a first gate electrode and a second gate electrode with the oxide semiconductor layer interposed therebetween.

7. A semiconductor device comprising the non-volatile latch circuit according to claim 1.

8. A non-volatile latch circuit comprising:

a first transistor;

a second transistor;

a first element including a third transistor;

a second element; and

a capacitor,

wherein an output of the first element is electrically connected to an input of the second element and an output of the second element is electrically connected to an input of the first element through the second transistor,

wherein the input of the first element is electrically connected to a wiring to which an input signal is applied through the first transistor and the output of the first element is electrically connected to a wiring to which an output signal is applied,

wherein one of a source electrode and a drain electrode of the first transistor is electrically connected to a gate of the third transistor, and the other of the source electrode and the drain electrode of the first transistor is electrically connected to the wiring to which the input signal is applied,

wherein one of a source electrode and a drain electrode of the second transistor is electrically connected to the gate of the third transistor, and the other of the source electrode and the drain electrode of the second transistor is electrically connected to the output of the second element,

wherein a channel formation region of each of the first transistor and the second transistor includes an oxide semiconductor layer, and

wherein the one of the source electrode and the drain electrode of the first transistor and the one of the source electrode and the drain electrode of the second transistor are electrically connected to one electrode of the capacitor.

9. The non-volatile latch circuit according to claim 8, wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

10. The non-volatile latch circuit according to claim 8, wherein data stored in the capacitor and a gate capacitance of the third transistor is retained by the first transistor and the second transistor.

11. The non-volatile latch circuit according to claim 8,

wherein the first element is a first inverter and the second element is a second inverter.

12. The non-volatile latch circuit according to claim 8,

wherein the first element is a NAND and the second element is a clocked inverter.

13. The non-volatile latch circuit according to claim 8,

wherein at least one of the first transistor and the second transistor comprises a first gate electrode and a second gate electrode with the oxide semiconductor layer interposed therebetween.

14. A semiconductor device comprising the non-volatile latch circuit according to claim 8.

15. A logic circuit comprising at least a first non-volatile latch circuit and a second non-volatile latch circuit,

wherein each of the first non-volatile latch circuit and the second non-volatile latch circuit comprising:

a first transistor;

a second transistor;

a first element including a third transistor; and

a second element,

wherein an output of the first element is electrically connected to an input of the second element and an output of the second element is electrically connected to an input of the first element through the second transistor,

wherein the input of the first element is electrically connected to a wiring to which an input signal is applied through the first transistor and the output of the first element is electrically connected to a wiring to which an output signal is applied,

wherein one of a source electrode and a drain electrode of the first transistor is electrically connected to a gate of the third transistor, and the other of the source electrode and the drain electrode of the first transistor is electrically connected to the wiring to which the input signal is applied,

wherein one of a source electrode and a drain electrode of the second transistor is electrically connected to the gate of the third transistor, and the other of the source electrode and the drain electrode of the second transistor is electrically connected to the output of the second element,

wherein a channel formation region of each of the first transistor and the second transistor includes an oxide semiconductor layer, and

wherein the wiring to which the input signal is applied of the second non-volatile latch circuit is electrically connected to the wiring to which the output signal is applied of the first non-volatile latch circuit.

16. The logic circuit according to claim 15, wherein the oxide semiconductor layer comprises indium, gallium, and zinc in each of the first non-volatile latch circuit and the second non-volatile latch circuit.

17. The logic circuit according to claim 15, wherein data stored in a gate capacitance of the third transistor is retained by the first transistor and the second transistor in each of the first non-volatile latch circuit and the second non-volatile latch circuit.

18. The logic circuit according to claim 15,

wherein the first element is a first inverter and the second element is a second inverter in the first non-volatile latch circuit or the second non-volatile latch circuit.

19. The logic circuit according to claim 15,

wherein the first element is a NAND and the second element is a clocked inverter in the first non-volatile latch circuit or the second non-volatile latch circuit.

20. The logic circuit according to claim 15,

wherein at least one of the first transistor and the second transistor comprises a first gate electrode and a second gate electrode with the oxide semiconductor layer interposed therebetween in the first non-volatile latch circuit or the second non-volatile latch circuit.

21. The logic circuit according to claim 15, further comprising a first capacitor in the first non-volatile latch circuit,

wherein the one of the source electrode and the drain electrode of the first transistor and the one of the source electrode and the drain electrode of the second transistor are electrically connected to one electrode of the first capacitor.

22. The logic circuit according to claim 15, further comprising a second capacitor in the second non-volatile latch circuit,

wherein the one of the source electrode and the drain electrode of the first transistor and the one of the source electrode and the drain electrode of the second transistor are electrically connected to one electrode of the second capacitor.

23. The logic circuit according to claim 15, further comprising a first capacitor in the first non-volatile latch circuit and a second capacitor in the second non-volatile latch circuit,

wherein the one of the source electrode and the drain electrode of the first transistor and the one of the source electrode and the drain electrode of the second transistor are electrically connected to one electrode of the first capacitor, and

wherein the one of the source electrode and the drain electrode of the first transistor and the one of the source electrode and the drain electrode of the second transistor are electrically connected to one electrode of the second capacitor.

24. A semiconductor device comprising the logic circuit according to claim 15.