SEMICONDUCTOR DEVICE
First Claim
1. A semiconductor device comprising:
- a first transistor;
a second transistor;
a first inverter circuit; and
a second inverter circuit,wherein one of a source and a drain of the first transistor is electrically connected to a first wiring;
wherein the other of the source and the drain of the first transistor is electrically connected to an input of the first inverter circuit;
wherein an output of the first inverter circuit is electrically connected to one of a source and a drain of the second transistor;
wherein the other of the source and the drain of the second transistor is electrically connected to an input of the second inverter circuit; and
wherein an output of the second inverter circuit is electrically connected to a second wiring.
1 Assignment
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Accused Products
Abstract
An object is to provide a low-power semiconductor device which does not require a latch circuit to hold data at the output of inverter circuits. In the semiconductor device, an input of a first inverter circuit is connected to an input terminal through a source and a drain of a first transistor. An input of a second inverter circuit is connected to an output of the first inverter circuit through a source and a drain of a second transistor. An output of the second inverter is connected to an output terminal. An inverted clock signal and a clock signal are input to gates of the first transistor and the second transistor, respectively. The first and the second transistor have extremely low off-current, which allows the output potential of the device to remain unchanged even when the input varies.
124 Citations
38 Claims
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1. A semiconductor device comprising:
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a first transistor; a second transistor; a first inverter circuit; and a second inverter circuit, wherein one of a source and a drain of the first transistor is electrically connected to a first wiring; wherein the other of the source and the drain of the first transistor is electrically connected to an input of the first inverter circuit; wherein an output of the first inverter circuit is electrically connected to one of a source and a drain of the second transistor; wherein the other of the source and the drain of the second transistor is electrically connected to an input of the second inverter circuit; and wherein an output of the second inverter circuit is electrically connected to a second wiring. - View Dependent Claims (6, 14, 19, 24, 29, 34)
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2. A semiconductor device comprising:
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a first transistor; a second transistor; a third transistor; a fourth transistor; a first inverter circuit; and a second inverter circuit, wherein the semiconductor device is configured to input a reset signal to a gate of the third transistor and a gate of the fourth transistor; wherein one of a source and a drain of the first transistor is electrically connected to a first wiring; wherein the other of the source and the drain of the first transistor is electrically connected to an input of the first inverter circuit; wherein an output of the first inverter circuit is electrically connected to one of a source and a drain of the second transistor; wherein the other of the source and the drain of the second transistor is electrically connected to an input of the second inverter circuit; wherein an output of the second inverter circuit is electrically connected to a second wiring; wherein one of a source and a drain of the third transistor is electrically connected to the input of the first inverter circuit; wherein the other of the source and the drain of the third transistor is electrically connected to a low voltage supply line; wherein one of a source and a drain of the fourth transistor is electrically connected to the input of the second inverter circuit; and wherein the other of the source and the drain of the fourth transistor is electrically connected to a high voltage supply line. - View Dependent Claims (7, 11, 15, 20, 25, 30, 35)
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3. A semiconductor device comprising:
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a first transistor; a second transistor; a fifth transistor; a sixth transistor; a first inverter circuit; and a second inverter circuit, wherein the semiconductor device is configured to input a set signal to a gate of the fifth transistor and a gate of the sixth transistor; wherein one of a source and a drain of the first transistor is electrically connected to a first wiring; wherein the other of the source and the drain of the first transistor is electrically connected to an input of the first inverter circuit; wherein an output of the first inverter circuit is electrically connected to one of a source and a drain of the second transistor; wherein the other of the source and the drain of the second transistor is electrically connected to an input of the second inverter circuit; wherein an output of the second inverter circuit is electrically connected to a second wiring; wherein one of a source and a drain of the fifth transistor is electrically connected to the input of the first inverter circuit; wherein the other of the source and the drain of the fifth transistor is electrically connected to a high voltage supply line; wherein one of a source and a drain of the sixth transistor is electrically connected to the input of the second inverter circuit; and wherein the other of the source and the drain of the sixth transistor is electrically connected to a low voltage supply line. - View Dependent Claims (8, 12, 16, 21, 26, 31, 36)
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4. A semiconductor device comprising:
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a first transistor; a second transistor; a third transistor; a fourth transistor; a fifth transistor; a sixth transistor; a first inverter circuit; and a second inverter circuit, wherein the semiconductor device is configured to input a reset signal to a gate of the third transistor and a gate of the fourth transistor; wherein the semiconductor device is configured to input a set signal to a gate of the fifth transistor and a gate of the sixth transistor; wherein one of a source and a drain of the first transistor is electrically connected to a first wiring; wherein the other of the source and the drain of the first transistor is electrically connected to an input of the first inverter circuit; wherein an output of the first inverter circuit is electrically connected to one of a source and a drain of the second transistor; wherein the other of the source and the drain of the second transistor is electrically connected to an input of the second inverter circuit; wherein an output of the second inverter circuit is electrically connected to a second wiring; wherein one of a source and a drain of the third transistor is electrically connected to the input of the first inverter circuit; wherein the other of the source and the drain of the third transistor is electrically connected to a low voltage supply line; wherein one of a source and a drain of the fourth transistor is electrically connected to the input of the second inverter circuit, and wherein the other of the source and the drain of the fourth transistor is electrically connected to a high voltage supply line; wherein one of a source and a drain of the fifth transistor is electrically connected to the input of the first inverter circuit; wherein the other of the source and the drain of the fifth transistor is electrically connected to the high voltage supply line; wherein one of a source and a drain of the sixth transistor is electrically connected to the input of the second inverter circuit; and wherein the other of the source and the drain of the sixth transistor is electrically connected to the low voltage supply line. - View Dependent Claims (9, 13, 17, 22, 27, 32, 37)
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5. A semiconductor device comprising:
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a first transistor; a second transistor; a first inverter circuit; a second inverter circuit; a first capacitor comprising a first pair of electrodes; and a second capacitor comprising a second pair of electrodes, wherein one of a source and a drain of the first transistor is electrically connected to a first wiring; wherein the other of the source and the drain of the first transistor is electrically connected to an input of the first inverter circuit, wherein an output of the first inverter circuit is electrically connected to one of a source and a drain of the second transistor, wherein the other of the source and the drain of the second transistor is electrically connected to an input of the second inverter circuit; wherein an output of the second inverter circuit is electrically connected to a second wiring; wherein one electrode of the first capacitor is electrically connected to the input of the first inverter circuit; wherein the other electrode of the first capacitor is electrically connected to a low voltage supply line; wherein one electrode of the second capacitor is electrically connected to the input of the second inverter circuit; and wherein the other electrode of the second capacitor is electrically connected to the low voltage supply line. - View Dependent Claims (10, 18, 23, 28, 33, 38)
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Specification