VARIABLE ATTENUATOR HAVING STACKED TRANSISTORS

• US 20110148501A1
• Filed: 12/23/2010
• Published: 06/23/2011
• Est. Priority Date: 12/23/2009
• Status: Active Grant

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: RF Micro Devices Incorporated (Qorvo, Inc.)
• Inventors: Granger-Jones, Marcus, Franzwa, Ed, Nelson, Brad
• Granted Patent: US 8,334,718 B2
• Time in Patent Office: Days
• US Class Current: 327/308
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49112 the connectors connecting a common bonding area on the semiconductor or solid-state body to different bonding areas outside the body, e.g. diverging wires
• CPC Class Codes: H01L 2224/49113 the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H03H 11/245 using field-effect transistor
• CPC Class Codes: H03L 5/00 Automatic control of voltage, current, or power

Abstract

In one embodiment, a variable attenuator is disclosed having an attenuation circuit and a control circuit. The attenuation circuit may include a first series connected attenuation circuit segment and a shunt connected attenuation circuit segment, as well as additional attenuation circuit segments. Each attenuation circuit segment includes a stack of transistors that are coupled to provide the attenuation circuit segment with a variable impedance level having a continuous impedance range. In this manner, the control circuit may be operably associated with the stack of transistors in each attenuation circuit segment to control the variable attenuation level of the variable attenuator.

Claims

1. An attenuator, comprising:

a first attenuation circuit having a first variable attenuation level that is adjustable within a first continuous attenuation range, the first attenuation circuit, comprising;

a first series connected attenuation circuit segment having a first plurality of stacked transistors, the first plurality of stacked transistors being coupled to provide the first series connected attenuation circuit segment with a first variable impedance level having a first continuous impedance range;

a first shunt connected attenuation circuit segment having a second plurality of stacked transistors, the second plurality of stacked transistors being coupled to provide the first shunt connected attenuation circuit segment with a second variable impedance level having a second continuous impedance range;

wherein the first variable attenuation level is based on the first variable impedance level and the second variable impedance level;

a control circuit adapted to receive an attenuation control signal, the control circuit being operably associated with the first plurality of stacked transistors to control the first variable impedance level based on a signal level of the attenuation control signal and the control circuit being operably associated with the second plurality of stacked transistors to control the second variable impedance level based on the signal level of the attenuation control signal.

2. The attenuator of claim 1, wherein the first attenuation circuit is formed on one or more substrates, each of the one or more substrates being selected from a group consisting of a silicon-on-insulator type substrate and a silicon-on-sapphire type substrate.

3. The attenuator of claim 1, wherein each of first and second plurality of transistors is selected from a group consisting of a complementary metal-oxide-semiconductor field effect transistor, a metal semiconductor field effect transistor, and a high electron mobility transistor.

4. The attenuator of claim 1, wherein the control circuit is operable to generate:

a first series segment control signal having a signal level related to the signal level of the attenuation control signal, the first plurality of stacked transistors being responsive to the first series segment control signal to set the first variable impedance level in accordance with the signal level of the first series segment control signal; and

a first shunt segment control signal, the second plurality of stacked transistors being responsive to the first shunt segment control signal to set the second variable impedance level in accordance with the signal level of the first shunt segment control signal.

5. The attenuator of claim 1, wherein the first series connected attenuation circuit segment further comprises:

a third plurality of stacked transistors each coupled in parallel with one of the first plurality of stacked transistors to also provide the first series connected attenuation circuit segment with the first variable impedance level having the first continuous impedance range;

wherein the control circuit is also operably associated with the third plurality of stacked transistors to control the first variable impedance level of the first series connected attenuation circuit segment based on the signal level of the attenuation control signal.

6. The attenuator of claim 1, wherein the first shunt connected attenuation circuit segment further comprises:

a third plurality of stacked transistors each coupled in parallel with one of the second plurality of stacked transistors to also provide the first shunt connected attenuation circuit segment with the second variable impedance level having the second continuous impedance range;

wherein the control circuit is also operably associated with the third plurality of stacked transistors to control the second variable impedance level based on the signal level of the attenuation control signal.

7. The attenuator of claim 1, wherein the first series connected attenuation circuit segment further comprises a first plurality of resistors each coupled in parallel with one of the first plurality of stacked transistors whereby the first variable impedance level of the first series connected attenuation circuit segment is related to a resistance of each of the first plurality of resistors.

8. The attenuator of claim 1, wherein the first shunt connected attenuation circuit segment further comprises a first plurality of resistors each coupled in parallel with more than one of the first plurality of stacked transistors whereby the second variable impedance level of the first shunt connected attenuation circuit segment is related to a resistance of each of the first plurality of resistors.

9. The attenuator of claim 1, further comprising:

a first resistive circuit coupled between the first plurality of stacked transistors and the control circuit, wherein the first resistive circuit has a resistance significantly above the first continuous impedance range of the first series connected attenuation circuit segment; and

a second resistive circuit coupled between the second plurality of stacked transistors and the control circuit, wherein the second resistive circuit has a resistance significantly above the second continuous impedance range of the first shunt connected attenuation circuit segment.

10. The attenuator of claim 1, further comprising a variable signal source operable to generate the attenuation control signal that has a variable signal level with a continuous signal range.

11. The attenuator of claim 10, wherein the variable signal source comprises a variable DC voltage source, the variable signal level being a variable voltage level and the continuous signal range being a continuous voltage range.

12. The attenuator of claim 1, wherein the first attenuation circuit further comprises:

an additional attenuation circuit segment having a third plurality of stacked transistors, the third plurality of stacked transistors being coupled to provide the additional attenuation circuit segment with a third variable impedance level having a third continuous impedance range;

wherein the first variable attenuation level is also based on the third variable impedance level;

wherein the first series connected attenuation circuit segment, the first shunt connected attenuation circuit segment, and the additional attenuation circuit segment are configured so that the first attenuation circuit is arranged in either a Tee type configuration or a Pi type configuration; and

wherein the control circuit is operably associated with the third plurality of stacked transistors to set the third variable impedance level based on the signal level of the attenuation control signal.

13. The attenuator of claim 12, further comprising:

an input terminal;

an output terminal, wherein the first attenuation circuit is coupled between the input terminal and the output terminal; and

wherein the control circuit is operable to set the first, second, and third variable impedance level so that the first variable attenuation level of the first attenuation circuit substantially matches an input impedance at the input terminal and an output impedance at the output terminal.

14. The attenuator of claim 13, wherein the first attenuation circuit is operable to provide matching by adjusting the input and output impedance.

15. The attenuator of claim 12, wherein:

the first plurality of stacked transistors comprise a first plurality of stacked field effect transistors (FETs);

the second plurality of stacked transistors comprises a second plurality of stacked FETs; and

the third plurality of stacked transistors comprises a third plurality of stacked FETs.

16. The attenuator of claim 15, wherein:

each of the first plurality of stacked FETs further comprises a source terminal, a drain terminal, and a gate terminal, wherein the source terminals and drain terminals of each of the first plurality of stacked FETS are coupled in series and the gate terminals of each of the first plurality of stacked FETS are coupled to the control circuit;

each of the second plurality of stacked FETs further comprises a source terminal, a drain terminal, and a gate terminal, wherein the source terminals and drain terminals of each of the second plurality of stacked FETS are coupled in series and the gate terminals of each of the second plurality of stacked FETS are coupled to the control circuit; and

each of the third plurality of stacked FETs further comprises a source terminal, an drain terminal, and a gate terminal, wherein the source terminals and drain terminals of each of the third plurality of stacked FETs are coupled in series and the gate terminals of each of the third plurality of stacked FETs are coupled to the control circuit.

17. The attenuator of claim 16, further comprising:

a first resistive circuit coupled between the gate terminals of each of the first plurality of stacked FETs and the control circuit, wherein the first resistive circuit has a high resistance relative to the first continuous impedance range such that a parasitic capacitance of each of the first plurality of stacked FETS is negligible when the first plurality of stacked FETs are operating in the first continuous impedance range;

a second resistive circuit coupled between the gate terminals of each of the second plurality of stacked transistors and the control circuit, wherein the second resistive circuit has a high resistance relative to the second continuous impedance range such that a parasitic capacitance of each of the second plurality of stacked FETS is negligible when the second plurality of stacked FETs are operating in the second continuous impedance range; and

a third resistive circuit coupled between the gate terminals of each of the third plurality of stacked transistors and the control circuit, wherein the third resistive circuit has a high resistance relative to the third continuous impedance range such that a parasitic capacitance of each of the third plurality of stacked FETS is negligible when the third plurality of stacked FETs are operating in the third continuous impedance range.

18. The attenuator of claim 17, wherein:

the first resistive circuit comprising a first plurality of resistors, wherein one or more of the first plurality of resistors are coupled in series with one of the gate terminals of one of the first plurality of stacked FETs;

the second resistive circuit comprising a second plurality of resistors, wherein one or more of the second plurality of resistors are coupled in series with one of the gate terminals of one of the second plurality of stacked FETs; and

the third resistive circuit comprising a third plurality of resistors, wherein one or more of the third plurality of resistors are coupled in series with one of the gate terminals of one of the third plurality of stacked FETs.

19. The attenuator of claim 17, wherein:

the first resistive circuit comprising a first plurality of resistors, wherein one or more of the first plurality of resistors are coupled between the gate terminals of one of the first plurality of stacked FETs and another one of the first plurality of stacked FETs;

the second resistive circuit comprising a second plurality of resistors, wherein one or more of the second plurality of resistors are coupled between the gate terminals of one of the second plurality of stacked FETs and another one of the second plurality of stacked FETs; and

the third resistive circuit comprising a third plurality of resistors, wherein one or more of the third plurality of resistors are coupled the gate terminals of one of the third plurality of stacked FETs and another one of the third plurality of stacked FETs.

20. The attenuator of claim 17, wherein each of the first, second, and third plurality of stacked FET are formed on one or more substrates, each of the one or more substrates being selected from a group consisting of a silicon-on-insulator type substrate and a silicon-on-sapphire type substrate.

21. The attenuator of claim 15, wherein:

each of the first, second, and third plurality of stacked FETs having a transistor body;

wherein the control circuit is operably associated to set a bias level of the transistor bodies of at least one of the first, second, and third plurality of plurality of stacked FETs.

22. The attenuator of claim 15, wherein:

each of the first, second, and third plurality of stacked FETs having a transistor body;

wherein the transistor bodies of at least one of the first, second, and third plurality of stacked FETs are coupled to a ground node.

23. The attenuator of claim 15, further comprising:

each of the first, second, and third plurality of stacked FETs having a transistor body;

a first biasing circuit coupled between the transistor bodies of the first plurality of stacked FETs;

a second biasing circuit coupled between the transistor bodies of the second plurality of stacked FETs; and

a third biasing circuit coupled between the transistor bodies of the second plurality of stacked FETs.

24. The attenuator of claim 1, further comprising:

a second attenuation circuit coupled to the first attenuation circuit, the second attenuation circuit having a second variable attenuation level that is adjustable within a second variable attenuation range, the second attenuation circuit comprising;

a second series connected attenuation circuit segment having a third plurality of stacked transistors, the third plurality of stacked transistors being coupled to provide the third series connected attenuation circuit segment with a third variable impedance level having a third continuous impedance range;

a second shunt connected attenuation circuit segment having a fourth plurality of stacked transistors, the second plurality of stacked transistors being coupled to provide the second shunt connected attenuation circuit segment with a fourth variable impedance level having a fourth continuous impedance range;

wherein the second variable attenuation level is based on the third variable impedance level and the fourth variable impedance level; and

wherein the control circuit is operably associated with the third plurality of stacked transistors to control the third variable impedance level of the second series connected attenuation circuit segment based on the signal level of the attenuation control signal and the control circuit is operably associated with the fourth plurality of stacked transistors to control the fourth variable impedance level of the second shunt connected attenuation circuit segment based on a signal level of the attenuation control signal.

25. The attenuator of claim 24, further comprising:

the first attenuation circuit further comprising a first additional attenuation circuit segment having a fifth plurality of stacked transistors, the fifth plurality of stacked transistors being coupled to provide the first additional attenuation circuit segment with a fifth variable impedance level having a fifth continuous impedance range, wherein the first series connected attenuation circuit segment, the first shunt connected attenuation circuit segment, and the first additional attenuation circuit segment are configured so that the first attenuation circuit is arranged as either a Pi type configuration or a Tee type configuration;

wherein the first variable attenuation level is also based on the third variable impedance level;

the second attenuation circuit further comprising a second additional attenuation circuit segment having a sixth plurality of stacked transistors, the sixth plurality of stacked transistors being coupled to provide the second additional attenuation circuit segment with a sixth variable impedance level within a sixth continuous impedance range, wherein the second series connected attenuation circuit segment, the second shunt connected attenuation circuit segment, and the second additional attenuation circuit segment are configured so that the second attenuation circuit is arranged as either a Pi type attenuation circuit or a Tee type attenuation circuit;

wherein the second variable attenuation level is also based on the sixth variable attenuation level; and

wherein the control circuit is operably associated with the fifth plurality of stacked transistors to control the fifth variable impedance level of the first additional attenuation circuit segment based on the signal level of the attenuation control signal and the control circuit is operably associated with the sixth plurality of stacked transistors to control the sixth variable impedance level based on the signal level of the attenuation control signal.

26. A method of varying an attenuation level of an attenuator, comprising:

providing a first attenuation circuit having a first variable attenuation level that is adjustable within a first continuous attenuation range, the first attenuation circuit including;

a first series connected attenuation circuit segment having a first plurality of stacked transistors that provide the first series connected attenuation circuit segment with a first variable impedance level having a first continuous impedance range;

a first shunt connected attenuation circuit segment having a second plurality of stacked transistors that provide the first shunt connected attenuation circuit segment with a second variable impedance level having a second continuous impedance range;

receiving an attenuation control signal;

adjusting the first variable attenuation level within the first continuous attenuation range by;

adjusting the first variable impedance level within the first continuous impedance range based on a signal level of the attenuation control signal; and

adjusting the second variable impedance level within the first continuous impedance range based on the signal level of the attenuation control signal.

27. The method of claim 26, wherein providing the first attenuation circuit further comprises forming the first attenuation circuit on a substrate, the substrate being selected from a group consisting of a silicon-over-insulator type substrate, a silicon-over-sapphire type substrate, and a gallium arsenide (GaAs) type substrate.

28. The method of claim 26, wherein:

wherein providing the first attenuation circuit further comprises;

providing a first additional attenuation circuit segment having a third plurality of stacked transistors that provide the first additional attenuation circuit segment with a third variable impedance level having a third continuous impedance range wherein the first series connected attenuation circuit segment, first shunt connected attenuation circuit segment, and the first additional attenuation circuit segment are arranged either in a Tee type configuration or a Pi type configuration;

wherein adjusting the first variable attenuation level further comprises adjusting the third variable impedance level of the additional attenuation circuit segment based on the signal level of the attenuation control signal.

29. The method of claim 28, matching an input impedance and an output impedance with the first attenuation circuit.

30. The method of claim 29, wherein matching the input impedance and the output impedance with the first attenuation circuit further comprises adjusting the input impedance and the output impedance.

31. An attenuator, comprising:

a first attenuation circuit having a first variable attenuation level that is adjustable within a first continuous attenuation range, the attenuator comprising;

a first series connected attenuation circuit segment having a first plurality of stacked transistors, the first plurality of stacked transistors being coupled to provide the first series connected attenuation circuit segment with a first variable impedance level having a first continuous impedance range;

a first shunt connected attenuation circuit segment having a second plurality of stacked transistors, the second plurality of stacked transistors being coupled to provide the first shunt connected attenuation circuit segment with a second variable impedance level having a second continuous impedance range;

wherein the first variable attenuation level is based on the first variable impedance level and the second variable impedance level;

a control circuit adapted to generate a first series segment control signal and a first shunt segment control signal, the control circuit being operably associated with the first plurality of stacked transistors to control the first variable impedance level of the first series connected attenuation circuit segment based on a signal level of the first series segment control signal and the control circuit being operably associated with the second plurality of stacked transistors to control the second variable impedance level of the first shunt connected attenuation circuit segment based on a signal level of the first shunt segment control signal.

32. The attenuator of claim 31, wherein the first attenuation circuit is formed on one or more substrates, each of the one or more substrates being selected from a group consisting of a silicon-over-insulator type substrate, a silicon-over-sapphire type substrate.

33. The attenuator of claim 31, wherein each of the first and second plurality of stacked transistors is selected from a group consisting of a complementary metal-oxide-semiconductor field effect transistor, a metal semiconductor field effect transistor, and a high electron mobility transistor.

34. The attenuator of claim 31, wherein:

the first attenuation circuit further comprises a second series connected attenuation circuit segment having a third plurality of stacked transistors, the third plurality of stacked transistors being coupled to provide the second series connected attenuation circuit segment with a third variable impedance level having a third continuous impedance range, wherein the first series connected attenuation circuit segment, first shunt connected attenuation circuit segment, and the second series connected attenuation circuit segment are arranged so that the first attenuation circuit is arranged in a Tee type configuration; and

wherein the first variable attenuation level is also based on the third variable impedance level.

35. The attenuator of claim 34, wherein the control circuit is operably associated with the third plurality of stacked transistors to control the third variable impedance level of the second series connected attenuation circuit segment based on the signal level of the first series segment control signal.

36. The attenuator of claim 34, wherein the control circuit is adapted to generate a second series segment control signal and the control circuit being operably associated with the third plurality of stacked transistors to control the third variable impedance level of the second series connected attenuation circuit segment based on a signal level of the second series segment control signal.

37. The attenuator of claim 31, wherein:

the first attenuation circuit further comprises a second shunt connected attenuation circuit segment having a third plurality of stacked transistors, the third plurality of stacked transistors being coupled to provide the second shunt connected attenuation circuit segment with a third variable impedance level having a third continuous impedance range, wherein the first series connected attenuation circuit segment, first shunt connected attenuation circuit segment, and the second shunt connected attenuation circuit segment are arranged so that the first attenuation circuit is arranged in a Pi type configuration; and

wherein the first variable attenuation level is also based on the third variable impedance level.

38. The attenuator of claim 37, wherein the control circuit is operably associated with the third plurality of stacked transistors to control the third variable impedance level of the second shunt connected attenuation circuit segment based on the signal level of the first shunt segment control signal.

39. The attenuator of claim 37, wherein the control circuit is adapted to generate a second shunt segment control signal and the control circuit being operably associated with the third plurality of stacked transistors to control the third variable impedance level of the second shunt connected attenuation circuit segment based on a signal level of the second shunt segment control signal.