Clock data recovery circuit, data transfer device for display device, and data transfer method for display device

• US 20110148851A1
• Filed: 12/20/2010
• Published: 06/23/2011
• Est. Priority Date: 12/22/2009
• Status: Abandoned Application

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Sugiyama, Akio, Nose, Takashi, Hori, Yoshihiko
• Application Number:
  US12/926,959
• Publication Number:
  US 20110148851A1
• Time in Patent Office: Days
• US Class Current: 345/213
• CPC Class Codes: G09G 2320/02 Improving the quality of display appearance
• CPC Class Codes: G09G 2320/0247 Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
• CPC Class Codes: G09G 2370/10 Use of a protocol of communication by packets in interfaces along the display data pipeline
• CPC Class Codes: G09G 3/2096 Details of the interface to the display terminal specific for a flat panel suitable for both CRT and flat panel G09G5/006; specific for a CRT G09G1/167
• CPC Class Codes: G09G 5/006 Details of the interface to the display terminal specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04

Abstract

A clock data recovery circuit includes a sampling circuit SC that samples input data by 2× over sampling, a frequency detection circuit FD that detects a frequency difference between the input data sampled by the sampling circuit SC and a recovery clock, a phase detection circuit PD that detects a phase difference between the input data sampled by the sampling circuit SC and the recovery clock, a voltage control oscillator circuit VCO that outputs the recovery clock to the sampling circuit SC at least according to the phase difference detected by the phase detection circuit PD, and a frequency detection control circuit FDC that stops an operation of the frequency detection circuit FD while receiving display data as the input data.

Claims

1. A clock data recovery circuit comprising:

a sampling circuit that samples input data by 2×

over sampling;

a frequency detection circuit that detects a frequency difference between the input data and a recovery clock, the input data being sampled by the sampling circuit;

a phase detection circuit that detects a phase difference between the input data and the recovery clock, the input data being sampled by the sampling circuit;

a voltage control oscillator circuit that outputs the recovery clock to the sampling circuit at least according to the phase difference detected by the phase detection circuit; and

a frequency detection control circuit that stops an operation of the frequency detection circuit while receiving display data as the input data.

2. The clock data recovery circuit according to claim 1, wherein the voltage control oscillator circuit outputs the recovery clock while the frequency detection circuit is operating according to the frequency difference detected by the frequency detection circuit in addition to the phase difference detected by the phase detection circuit.

3. The clock data recovery circuit according to claim 1, wherein the input data while the frequency detection circuit is operating is specified in a way that a pattern in which a same level signal continues for only two bits is less than or equal to a predetermined number.

4. The clock data recovery circuit according to claim 1, wherein the frequency detection control circuit stops the operation of the frequency detection circuit in response to a data start signal.

5. The clock data recovery circuit according to claim 1, wherein

time for the display data is previously determined, and

the frequency detection circuit resumes the operation after predetermined time following the stop of the operation.

6. A data transfer apparatus for a display device comprising:

a timing controller that transmits transfer data; and

a display element driver circuit that receives the transfer data, the transfer data being transmitted from the timing controller, wherein the display element driver circuit comprises;

a sampling circuit that samples input data by 2×

over sampling;

a frequency detection circuit that detects a frequency difference between the input data and a recovery clock, the input data being sampled by the sampling circuit;

a phase detection circuit that detects a phase difference between the input data and the recovery clock, the input data being sampled by the sampling circuit;

a voltage control oscillator circuit that outputs the recovery clock to the sampling circuit at least according to the phase difference detected by the phase detection circuit; and

a frequency detection control circuit that stops an operation of the frequency detection circuit while receiving display data as the input data.

7. The data transfer apparatus according to claim 6, wherein the voltage control oscillator circuit outputs the recovery clock while the frequency detection circuit is operating according to the frequency difference detected by the frequency detection circuit in addition to the phase difference detected by the phase detection circuit.

8. The data transfer apparatus according to claim 6, wherein the transfer data while the frequency detection circuit is operating is specified in a way that a pattern in which a same level signal continues for only two bits is less than or equal to a predetermined number.

9. A data transfer method for a display device that transfers data from a timing controller to a display element driver circuit, the data transfer method comprising:

sampling transfer data by 2×

over sampling;

detecting a phase difference between the sampled transfer data and a recovery clock instead of a frequency difference while the transfer data is display data so as to generate the recovery clock;

detecting the frequency difference and the phase difference of the sampled transfer data while the transfer data is not the display data so as to generate the recovery clock.

10. The data transfer method according to claim 9, wherein the transfer data except the display data is specified in a way that a pattern in which a same level signal continues for only two bits is less than or equal to a predetermined frequency.