Data Transfer Flows for On-Chip Folding

• US 20110149650A1
• Filed: 12/18/2009
• Published: 06/23/2011
• Est. Priority Date: 12/18/2009
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Hutchison, Neil David, Huang, Jianmin, Avila, Chris, Gorobets, Sergey Anatolievich, Gavens, Lee M.
• Granted Patent: US 8,144,512 B2
• Time in Patent Office: Days
• US Class Current: 365/185.03
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 2211/5643 Multilevel memory comprising cache storage devices
• CPC Class Codes: G11C 7/1042 using interleaving techniques, i.e. read-write of one part of the memory while preparing another part

Abstract

A memory system and methods of its operation are presented. The memory system includes a volatile buffer memory and a non-volatile memory circuit, where the non-volatile memory circuit has a first section, where data is stored in a binary format, and a second section, where data is stored in a multi-state format. When writing data to the non-volatile memory, the data is received from a host, stored in the buffer memory, transferred from the buffer memory to into read/write registers of the non-volatile memory circuit, and then written from the read/write registers to the first section of the non-volatile memory circuit using a binary write operation. Portions of the data and then subsequently folded from the first section of the non-volatile memory to the second section of the non-volatile memory, where a folding operation includes reading the portions of the data from multiple locations in the first section into the read/write registers and performing a multi-state programming operation of the potions of the data from the read/write registers into a location the second section of the non-volatile memory. The multi-state programming operations include a first phase and a second phase and one or more of the binary write operations are performed between the phases of the multi-state programming operations.

Claims

1. A method of operating a memory system including a volatile buffer memory and a non-volatile memory circuit, the non-volatile memory circuit having a first section, where data is stored in a binary format, and a second section, where data is stored in a multi-state format, the method comprising:

receiving data from a host;

storing the received data in the buffer memory;

transferring the data from the buffer memory to read/write registers of the non-volatile memory circuit;

performing a binary write operation of the data from the read/write registers to the first section of the non-volatile memory circuit; and

subsequently folding portions of the data from the first section of the non-volatile memory to the second section of the non-volatile memory, wherein a folding operation includes;

reading the portions of the data from multiple locations in the first section into the read/write registers; and

performing a multi-state programming operation of the portions of the data from the read/write registers into a location of the second section of the non-volatile memory,

wherein the multi-state programming operations include a first phase and a second phase and one or more binary write operations are performed between the phases of the multi-state programming operations.

2. The method of claim 1, wherein the second section store data in an N-bit per cell format,

wherein the data received from the host corresponds to multiple logical pages of data and the binary write operation stores each of the logical pages of data from the read/write registers to a physical page in the first section of the non-volatile memory circuit, and

wherein the folding operation includes:

reading N logical pages from a corresponding N physical pages in the first section into the data read/write registers; and

performing the multi-state programming operation of the N logical pages of data from the read/write registers into a physical page of the second section of the non-volatile memory.

3. The method of claim 1, wherein one or more binary write operations are performed subsequent to one of the first phases and prior to a following second phase.

4. The method of claim 1, wherein one or more binary write operations are performed subsequent to one of the second phases and prior to a following first phase.

5. The method of claim 1, wherein the transfers of data from the host to the buffer memory are performed concurrently with multi-state programming operations.

6. The method of claim 1, where the memory system further includes a controller circuit that manages the storage of data on the non-volatile memory circuit and the transfer of data between the memory system and a host system, and wherein the buffer memory is part of the controller circuit.

7. The method of claim 1, wherein the non-volatile memory circuit comprises a plurality of non-volatile memory cells formed along a plurality of word lines and a plurality of bits lines formed as plurality of erase blocks, and wherein the physical pages of the first and second sections belong to differing erase blocks that share a common set of bit lines.

8. The method of claims 1, wherein the multi-state programming operation uses a foggy-fine programming algorithm and the first phase includes a foggy programming operation and the second phase is a fine programming operation.

9. The method of claims 8, wherein the first phase further includes an initial programming operation prior to the foggy programming operation.

10. The method of claim 1, wherein the transfers of data from the host to the buffer memory are performed concurrently with the first and second phases of multi-state programming operations.

11. The method of claim 1, wherein the memory system includes multiple semi-autonomous non-volatile memory arrays, wherein binary write operations and the folding of pages are performed in parallel on a plurality of the semi-autonomous non-volatile memory arrays.