Methods and Apparatus for Write-Side Intercell Interference Mitigation in Flash Memories

• US 20110149657A1
• Filed: 06/30/2009
• Published: 06/23/2011
• Est. Priority Date: 07/01/2008
• Status: Active Grant

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: LSI Corporation (Broadcom, Inc.)
• Inventors: Ivkovic, Milos, Haratsch, Erich F., Krachkovsky, Victor, Vityaev, Andrei, Yen, Johnson, Miladinovic, Nenad
• Granted Patent: US 8,526,230 B2
• Time in Patent Office: Days
• US Class Current: 365/185.18
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

Methods and apparatus are provided for write-side intercell interference mitigation in flash memories. A flash memory device is written by obtaining program data to be written to at least one target cell in the flash memory; obtaining one or more bits of program data for at least one aggressor cell to be programmed later than the target cell: and precompensating for intercell interference for the target cell by generating precompensated program values. The aggressor cells comprise one or more cells adjacent to the target cell, such as adjacent cells in a same wordline as the target cell and/or cells in an upper or lower adjacent wordline to the target cell. The precompensated program values for the target cell are optionally provided to the flash memory.

Claims

1. A method for writing to a flash memory device, comprising:

obtaining program data to be written to at least one target cell in said flash memory;

obtaining one or more bits of program data for at least one aggressor cell to be programmed later than said target cell; and

precompensating for intercell interference for said target cell by generating precompensated program values.

2. The method of claim 1, wherein said flash memory device is programmed using one or more of a page access technique and a wordline level access technique.

3. The method of claim 1, wherein said at least one aggressor cell comprises one or more cells adjacent to said target cell.

4. The method of claim 3, wherein said at least one aggressor cell comprises one or more adjacent cells in a same wordline as said target cell.

5. The method of claim 3, wherein said at least one aggressor cell comprises one or more cells in an upper or lower adjacent wordline to said target cell.

6. The method of claim 3, wherein at least one of said at least one aggressor cells is stored in a buffer until all of said at least one aggressor cells are available.

7. The method of claim 3, wherein said at least one aggressor cell is identified by analyzing a programming sequence scheme employed for said flash memory device.

8. The method of claim 1, wherein a new program voltage of said target cell that precompensates for said intercell interference is obtained with following equation:

PV_tc^(i,j)=PV_t^(i,j)−

Δ

V_c 

 

(2)

where PV_t is the original program voltage;

PV_tc is the new program voltage after ICI cancellation and Δ

V_c is the ICI cancellation term.

9. The method of claim 8, wherein said intercell interference mitigation term can be computed as follows:

Δ

V_c^(i,j)=k_xΔ

V_t<sup>(i,j−

1)</sup>(l)+k_xΔ

V_t^(i,j+1)(l)+k_yΔ

V_t^(i+1,j)(l)+k_xyΔ

V_t<sup>(i+1,j−

1)</sup>(l)+k_xyΔ

V_t^(i+1,j+1)(l) 

 

(3)

where Δ

V_t^(w,b)(l) is the change in the V_t of cell (w,b) when voltage level l is programmed into cell (w,b);

lε

{1, 2, . . . L} is the voltage level; and

k_x,k_y, and k_xy are the capacitive coupling coefficients. Note that different voltage levels l can be programmed into the different target and agressor cells.

10. The method of claim 1, further comprising the step of providing said precompensated program values for said target cell on an interface for writing in a memory array of said flash memory device.

11. The method of claim 1, wherein said obtaining steps obtain said program data to be written to at least one target cell and said one or more bits of program data for at least one aggressor cell from an interface and said precompensated program values are computed by a processor associated with said flash memory device.

12. The method of claim 1, wherein said method is applied to one or more steps of a multi-step page programming sequence.

13. The method of claim 1, wherein said step of determining intercell interference neglects intercell interference for said target cell from diagonally adjacent aggressor cells.

14. The method of claim 1, wherein said step of determining intercell interference neglects intercell interference for said target cell from one or more adjacent cells in the same wordline for an even/odd programming sequence.

15. The method of claim 1, further comprising the step of providing said precompensated program values for said target cell to the flash memory.

16. The method of claim 1, wherein voltage shift properties of a multi-step programming sequence are employed to reduce a number of distinct voltage shifts Δ

V_c values in to be computed to M^k, wherein M<

L, k is a number of considered aggressor cells and M is the number of distinct voltage shifts that are considered.

17. A system for writing to a flash memory device, comprising:

a memory; and

at least one processor, coupled to the memory, operative to;

obtain program data to be written to at least one target cell in said flash memory;

obtain one or more bits of program data for at least one aggressor cell to be programmed later than said target cell; and

precompensate for intercell interference for said target cell by generating precompensated program values.