MULTIPLYING AND ADDING MATRICES

• US 20110153707A1
• Filed: 12/10/2010
• Published: 06/23/2011
• Est. Priority Date: 12/23/2009
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Rubanovich, Simon, Ginzburg, Boris, Eitan, Benny
• Granted Patent: US 8,984,043 B2
• Time in Patent Office: Days
• US Class Current: 708/523
• CPC Class Codes: G06F 17/16 Matrix or vector computation , e.g. matrix-matrix or matrix-vector multiplication, matrix factorization matrix transposition G06F7/78
• CPC Class Codes: G06F 9/3001 Arithmetic instructions
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations

Abstract

An apparatus and method are described for multiplying and adding matrices. For example, one embodiment of a method comprises decoding by a decoder in a processor device, a single instruction specifying an m-by-m matrix operation for a set of vectors, wherein each vector represents an m-by-m matrix of data elements and m is greater than one; issuing the single instruction for execution by an execution unit in the processor device; and responsive to the execution of the single instruction, generating a resultant vector, wherein the resultant vector represents an m-by-m matrix of data elements.

Claims

1. A method comprising:

decoding by a decoder in a processor device, a single instruction specifying an m-by-m matrix operation for a set of vectors, wherein each vector represents an m-by-m matrix of data elements and m is greater than one;

issuing the single instruction for execution by an execution unit in the processor device; and

responsive to the execution of the single instruction, generating a resultant vector, wherein the resultant vector represents an m-by-m matrix of data elements.

2. The method of claim 1, wherein the matrix operation is a matrix multiply-add operation.

3. The method of claim 1, wherein the set of vectors comprises a first vector, a second vector, and a third vector.

4. The method of claim 3, wherein the first vector represents an m-by-m matrix of data elements stored in a row ordered format, the second vector represents an m-by-m matrix of data elements stored in a column ordered format, and the third vector represents an m-by-m matrix of data elements stored in a row ordered format.

5. The method of claim 3, wherein generating the resultant vector comprises:

multiplying data elements corresponding to a first row in the first vector with data elements corresponding to a first column in the second vector to generate a set of intermediate results; and

adding the set of intermediate results to generate a first result data element.

6. The method of claim 5, wherein the set of intermediate results comprises a first intermediate result, a second intermediate result, a third intermediate result, and a fourth intermediate result, and wherein multiplying data elements corresponding to the first row in the first vector with data elements corresponding to the first column in the second vector to generate the set of intermediate results comprises:

performing a fused multiply-add operation to generate the first intermediate result by multiplying a first data element of the first vector with a corresponding data element of the second vector, and adding a corresponding data element of the third vector; and

performing a multiply operation to generate the second, third, and fourth intermediate results.

7. The method of claim 5, wherein m equals four and wherein generating the resultant vector further comprises:

multiplying data elements corresponding to a second row in the first vector with data elements corresponding to a first column in the second vector to generate a second set of intermediate results;

multiplying data elements corresponding to a third row in the first vector with data elements corresponding to a first column in the second vector to generate a third set of intermediate results; and

multiplying data elements corresponding to a fourth row in the first vector with data elements corresponding to a first column in the second vector to generate a fourth set of intermediate results.

8. The method of claim 7, wherein generating the resultant vector further comprises:

adding the second set of intermediate results to generate a second result data element;

adding the third set of intermediate results to generate a third result data element; and

adding the fourth set of intermediate results to generate a fourth result data element;

wherein the first, second, third, and fourth result data elements represent a first row of data elements in the m-by-m matrix represented by the resultant vector

9. A processor device comprising:

a storage location configured to store a first set of data elements, a second set of data elements, and a third set of data elements, wherein the first, second, and third sets of data elements represent respective m-by-m matrices and m is greater than one;

a decoder configured to decode a single instruction specifying an m-by-m matrix multiply-add operation; and

an execution unit coupled to the decoder to receive decoded instructions and coupled to the storage location to execute the m-by-m matrix multiply-add operation;

wherein, responsive to executing the m-by-m matrix multiply-add operation, the execution unit is configured to generate a resultant vector representing an m-by-m result matrix.

10. The processor device of claim 9, wherein the execution unit comprises m sub-units, the sub-units operable to generate a respective portion of the resultant vector, each portion representing a row of the m-by-m result matrix.

11. The processor device of claim 10, wherein m is equal to four.

12. The processor device of claim 10, wherein each of the m sub-units comprises:

a plurality of multiplier devices configured to multiply data elements corresponding to a row in a first m-by-m matrix represented by the first set of data elements with data elements corresponding to a column in a second m-by-m matrix represented by the second set of data elements.

13. The processor device of claim 12, wherein the plurality of multiplier devices comprise a fused multiply-add unit configured to multiply a data element from the first set of data elements with a data element from the second set of data elements to generate an intermediate result and to add a data element from the third set of data elements to the intermediate result.

14. The processor device of claim 10, wherein each of the m sub-units further comprises a plurality of adders configured to add a plurality of intermediate results to generate a first result data element.

15. A system comprising:

a memory controller coupled to a first storage location configured to store a first set of data elements; and

a processor coupled to the memory controller, the processor comprising;

a register file unit configured to store a second set of data elements, and a third set of data elements, wherein the first, second, and third sets of data elements represent respective m-by-m data matrices;

a decoder configured to decode a single instruction specifying an m-by-m matrix multiply-add operation; and

an execution unit coupled to the decoder to receive decoded instructions and coupled to the first storage location and register file unit to execute the m-by-m matrix multiply-add operation;

wherein, responsive to executing the m-by-m matrix multiply-add operation, the execution unit is configured to generate a resultant vector representing an m-by-m result matrix.

16. The system of claim 15, wherein m is equal to four.

17. The system of claim 15, wherein the execution unit comprises m sub-units, the sub-units operable to generate a respective portion of the resultant vector, each portion representing a row of the m-by-m result matrix.

18. The processor device of claim 17, wherein each of the m sub-units comprises:

a plurality of multipliers configured to multiply data elements corresponding to a row in a first m-by-m matrix represented by the first set of data elements with data elements corresponding to a column in a second m-by-m matrix represented by the second set of data elements.