Source Core Interrupt Steering

• US 20110153893A1
• Filed: 12/18/2009
• Published: 06/23/2011
• Est. Priority Date: 12/18/2009
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Veal, Bryan E., Foong, Annie
• Granted Patent: US 8,321,615 B2
• Time in Patent Office: Days
• US Class Current: 710/268
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: G06F 9/4812 by interrupt, e.g. masked

Abstract

An embodiment of the invention includes (i) receiving a core identifier that corresponds with a processor source core; (ii) receiving an input/output request, produced from the source core, that is associated with the core identifier; (iii) and directing an interrupt, which corresponds to the request, to the source core based on the core identifier. Other embodiments are described herein.

Claims

1. A method comprising:

receiving a core identifier that corresponds with a source core, wherein the source core is included in a processor;

receiving an input/output request, produced from the source core, that is associated with the core identifier;

storing the core identifier in a memory coupled to the processor; and

directing an interrupt, which corresponds to the request, to the source core based on the core identifier;

wherein the processor is coupled to an additional core.

2. The method of claim 1 including directing the interrupt to the source core, but not the additional core, based on the core identifier.

3. The method of claim 2, wherein the request includes the core identifier.

4. The method of claim 2 further comprising directing a message-signaled interrupt message to the source core based on the core identifier.

5. The method of claim 1 including determining a message-signaled interrupt address based on the core identifier.

6. The method of claim 1 including storing the core identifier in the memory before directing the interrupt to the source core.

7. The method of claim 1, wherein the request includes a message-signaled interrupt address.

8. The method of claim 7 including directing the interrupt to the source core independently of a message-signaled interrupt table.

9. The method of claim 7 including changing a message-signaled interrupt vector, which is included in the request, after the request has been sent from the source core.

10. The method of claim 7 including directing a message-signaled interrupt message, which includes the message-signaled interrupt address, to the source core.

11. The method of claim 1 including:

receiving an additional core identifier that corresponds with the source core;

receiving an additional input/output request, produced from the source core, that is associated with the additional core identifier; and

coalescing the request and additional request based on an affiliation between the core identifier and the additional core identifier.

12. An article comprising a medium storing instructions that enable a processor-based system to:

receive a core identifier (CID) that corresponds with a source core, wherein the source core is included in a processor;

receive an input/output request, produced from the source core, that is associated with the core identifier; and

steer an interrupt, which corresponds to the request, to the source core based on the core identifier;

wherein the processor is coupled to an additional core.

13. The article of claim 12 further storing instructions that enable the system to steer the interrupt to the source core, but not the additional core, based on the CID.

14. The article of claim 13 further storing instructions that enable the system to steer a message-signaled interrupt (MSI) message to the source core based on the CID.

15. The article of claim 13 further storing instructions that enable the system to steer a message-signaled interrupt (MSI) message to the source core independently of a MSI table, wherein a portion of the MSI message is included in the request.

16. A method comprising:

using a first queue identifier (QID) to associate a first controller request queue with a first processor core;

using a second QID to associate a second controller request queue with a second processor core;

storing a first input/output (I/O) request, which is produced from the first core and is associated with the first QID, in the first queue based on the first QID; and

directing a first interrupt, which corresponds to the first request, to one of the first and second cores based on the first QID.

17. The method of claim 16 including directing the first interrupt to the first core, but not the second core, based on the first QID.

18. The method of claim 17 further comprising directing a message-signaled interrupt (MSI) message, corresponding to the first request, to the first core based on the first QID.

19. The method of claim 18 including determining a MSI address based on the first QID.

20. The method of claim 16 including:

storing an second input/output (I/O) request, which is produced from the second core and is associated with the second QID, in the second queue based on the second QID; and

directing a second interrupt, which corresponds to the second request, to the second core based on the second QID.