DEVICE, SYSTEM, AND METHOD FOR REDUCING PROGRAM/READ DISTURB IN FLASH ARRAYS

• US 20110153919A1
• Filed: 12/15/2010
• Published: 06/23/2011
• Est. Priority Date: 12/22/2009
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: DensBits Technologies Ltd. (Broadcom, Inc.)
• Inventors: SABBAG, Erez
• Granted Patent: US 9,037,777 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 2211/5648 Multilevel memory programming, reading or erasing operations wherein the order or sequence of the operations is relevant

Abstract

A method, device and computer readable medium for programming a nonvolatile memory block. The method may include programming information, by a memory controller, to the nonvolatile memory block by performing a sequence of programming phases of descending bit significances. The device may include a nonvolatile memory block; and a memory controller that may be configured to determine a bit significance level of the nonvolatile memory block; program the nonvolatile memory block by performing at least one programming phase; and program the nonvolatile memory block to an erase value that may be higher than the pre-erase value; wherein the erase value and the pre-erase value may be selected based on the bit significance level of the nonvolatile memory block. The method may include packing three single level cell (SLC) nonvolatile memory blocks to one three-bit per cell nonvolatile memory block in order of the three SLC bit significances.

Claims

1. A method for programming a nonvolatile memory block, the method comprising:

programming information, by a memory controller, to pages in the nonvolatile memory block by performing a sequence of programming phases in order of descending bit significances, wherein all pages of the same bit significance are programmed prior to pages having a descending bit significance.

2. The method of claim 1, wherein the sequence of programming phases starts from a most significant bit programming phase and ends at a least significant bit programming phase.

3. The method of claim 1, including programming nonvolatile memory rows of the nonvolatile memory block during the sequence of programming phases.

4. The method of claim 1, wherein a row programming order of at least two programming phases of the sequence of programming phases differ from each other.

5. The method of claim 1, wherein at least one programming phase of the sequence of programming phases exhibits an ascending row programming order and at least another programming phase of the sequence of programming phases exhibits a descending row programming order.

6. The method of claim 1, wherein at least one programming phase of the sequence of programming phases exhibits an interleaved row programming order.

7. The method of claim 1, wherein at least one programming phase of the sequence of programming phases exhibits an interleaved row programming order between odd and even nonvolatile memory blocks.

8. The method of claim 1, wherein at least two programming phases of the sequence of programming phases have a same row programming order.

9. The method of claim 1, wherein at least two programming phases of the sequence of programming phases differ in a level of pass voltage that is supplied to idle nonvolatile memory rows.

10. The method of claim 9, wherein a level of the pass voltage decreases as a bit significance of a programming phase decreases.

11. The method of claim 1, comprising programming information retrieved from a set of nonvolatile single level memory blocks to a single nonvolatile memory block by performing a sequence of programming phases of descending bit significances.

12. The method of claim 1, wherein each programming phase comprises programming the nonvolatile memory block to a pre-erase value, and the method further comprises programming the nonvolatile memory block to an erase value that is higher than the pre-erase value.

13. The method of claim 12, wherein at least two programming phases differ in the pre-erase value.

14. The method of claim 12, wherein a level of the pre-erase value decreases with a decrement of a bit significant of a programming phase.

15. The method of claim 12, comprising calculating a wear attribute of the nonvolatile memory block by associating different count weights to different programming phases that program the nonvolatile memory block to the erase value.

16. The method of claim 1, comprising:

determining a bit significance level of the nonvolatile memory block; and

starting the sequence of programming phases from a programming phase that corresponds to the bit significance level of the nonvolatile memory block.

17. The method of claim 1, comprising reading the information, by the memory controller, from the nonvolatile memory block by performing a sequence of read phases of descending bit significances, starting from a most significant bit programming phase and ending at a least significant bit programming phase.

18. The method of claim 1, comprising programming information, by the memory controller, to multiple nonvolatile memory blocks, wherein each nonvolatile memory block is programmed by performing a sequence of programming phases of descending bit significances.

19. The method of claim 18, wherein at least two nonvolatile memory blocks belong to different integrated circuits.

20. The method of claim 1, further including:

packing three single level cell (SLC) nonvolatile memory blocks to one three-bit per cell nonvolatile memory block by programming information of a first SLC nonvolatile memory block by a MSB programming phase, programming information of a second SLC nonvolatile memory block by a CSB programming phase, and programming the information of a third SLC nonvolatile memory block by a LSB programming phase.

21. A method for erasing a nonvolatile memory block, the method comprising:

determining a bit significance level of one or more memory pages within the nonvolatile memory block; and

programming the nonvolatile memory block by performing at least one programming phase, wherein each programming phase comprises programming the nonvolatile memory block to an erase value that is higher than the pre-erase value, wherein the erase value and the pre-erase value are selected based on the bit significance level of the one or more memory pages within the nonvolatile memory block.

22. A device having programming capabilities, the device comprising:

a nonvolatile memory block; and

a memory controller configured to program information to pages in the nonvolatile memory block by performing a sequence of programming phases of descending bit significances, wherein all pages of the same bit significance are programmed prior to pages having a descending bit significance.

23. The device of claim 22, wherein the sequence of programming phases of descending bit significances starts from a most significant bit programming phase and ends at a least significant bit programming phase.

24. The device of claim 22, wherein the memory controller is configured to program the nonvolatile memory rows of the nonvolatile memory block during each programming phase of the sequence.

25. The device of claim 22, wherein at least two programming phases of the sequence differ by row programming order from each other.

26. The device of claim 22, wherein one programming phase of the sequence exhibits an ascending row programming order and another programming phase of the sequence exhibits a descending row programming order.

27. The device of claim 22, wherein at least one programming phase of the sequence exhibits an interleaved row programming order.

28. The device of claim 22, wherein at least one programming phase of the sequence exhibits an interleaved row programming order between odd and even nonvolatile memory blocks.

29. The device of claim 22, wherein at least two programming phases of the sequence have a same row programming order.

30. The device of claim 22, wherein at least two programming phases of the sequence differ in a level of pass voltage supplied to idle nonvolatile memory rows.

31. The device of claim 30, wherein the pass voltage level decreases as bit significance of a programming phase decreases.

32. The device of claim 22, wherein the memory controller is configured to program information retrieved from a set of nonvolatile single level memory blocks to a single nonvolatile memory block by performing the sequence of programming phases of descending bit significances.

33. The device of claim 22, wherein the memory controller is configured to program the nonvolatile memory block to a pre-erase value, and program the nonvolatile memory block to an erase value that is higher than the pre-erase value, during each programming phase.

34. The device of claim 32, wherein at least two programming phases differ in the pre-erase value.

35. The device of claim 33, wherein the pre-erase value decreases with a decrement of a bit significance of a programming phase.

36. The device of claim 32, wherein the memory controller is configured to calculate a wear attribute of the nonvolatile memory block by associating different count weights to different programming phases that program the nonvolatile memory block to the erase value.

37. The device of claim 22, wherein the memory controller is configured to:

determine a bit significance level of the nonvolatile memory block; and

start the sequence of programming phases from a programming phase that corresponds to the bit significance level of the nonvolatile memory block.

38. The device of claim 22, wherein the memory controller is configured to read the information from the nonvolatile memory block by a performing a sequence of read phases of descending bit significances, starting from a most significant bit programming phase and ending at a least significant bit programming phase.

39. The device of claim 22, wherein the memory controller is configured to program multiple nonvolatile memory block, wherein each nonvolatile memory block is programmed by performing a sequence of programming phases of descending bit significances.

40. The device of claim 39, wherein at least two nonvolatile memory blocks belong to different integrated circuits.

41. The device of claim 22, wherein the memory controller is configured to pack three single level cell (SLC) nonvolatile memory blocks to one three-bit per cell nonvolatile memory block.

42. A device, comprising:

a nonvolatile memory block; and

a memory controller configured to;

determine a bit significance level of one or more memory pages in the nonvolatile memory block;

program the one or more memory pages within the nonvolatile memory block by performing at least one programming phase, wherein the memory controller is configured to program the one or more memory pages within the nonvolatile memory block to an erase value that is higher than the pre-erase value, during each programming phase, wherein the erase value and the pre-erase value are selected based on the bit significance level of the one or more memory pages within the nonvolatile memory block.

43. A computer readable medium for storing instructions for:

determining a bit significance level of one or more memory pages within a nonvolatile memory block;

programming the one or more memory pages within the nonvolatile memory block by performing at least one programming phase, wherein each programming phase comprises programming the one or more memory pages within the nonvolatile memory block to an erase value that is higher than the pre-erase value, wherein the erase value and the pre-erase value are selected based on the bit significance level of the one or more memory pages.

44. A computer readable medium for storing instructions for programming information, by a memory controller, to one or more memory pages within a nonvolatile memory block by performing a sequence of programming phases based on the descending bit significances of the one or more memory pages.

45. A computer readable medium for storing instructions for

packing three single level cell (SLC) nonvolatile memory blocks to one three-bit per cell nonvolatile memory block by programming information of a first SLC nonvolatile memory block by a MSB programming phase, programming information of a second SLC nonvolatile memory block by a CSB programming phase, and programming the information of a third SLC nonvolatile memory block by a LSB programming phase.