MULTI-COLUMN ADDRESSING MODE MEMORY SYSTEM INCLUDING AN INTEGRATED CIRCUIT MEMORY DEVICE
First Claim
1. An integrated circuit memory device, comprising:
- a storage array having storage cells arranged in plural rows and plural columns;
a row decoder to select a row of storage cells within the storage array;
column decoder circuitry to select one or more of the plural columns in the selected row in response to one or more externally supplied column addresses; and
an interface to couple the integrated circuit memory device with an external interconnect;
wherea minimum time interval comprising a minimum number of clock cycles must elapse between successive accesses to an open row of storage cells in the storage array, andthe memory device outputs data read from the open row, in response to two different externally supplied column addresses, to the external interconnect via the interface during a time period less than twice the minimum time interval.
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Abstract
A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface.
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Citations
33 Claims
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1. An integrated circuit memory device, comprising:
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a storage array having storage cells arranged in plural rows and plural columns; a row decoder to select a row of storage cells within the storage array; column decoder circuitry to select one or more of the plural columns in the selected row in response to one or more externally supplied column addresses; and an interface to couple the integrated circuit memory device with an external interconnect;
wherea minimum time interval comprising a minimum number of clock cycles must elapse between successive accesses to an open row of storage cells in the storage array, and the memory device outputs data read from the open row, in response to two different externally supplied column addresses, to the external interconnect via the interface during a time period less than twice the minimum time interval. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. An integrated circuit memory device, comprising:
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a storage array having storage cells arranged in plural rows and plural columns; a row decoder to select a row of storage cells within the storage array; an interface to couple the integrated circuit memory device with an external interconnect; and circuitry to decode two or more independent column addresses received via the interface as part of a common request packet. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25, 26)
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27. An integrated circuit memory device, comprising:
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a storage array having storage cells arranged in plural rows and plural columns; a row decoder to select a row of storage cells within the storage array; where a minimum time interval comprising a minimum number of clock cycles must elapse between successive accesses to an open row of storage cells in the storage array; and means for outputting read data from the open row and from the integrated circuit memory device in response to two different externally supplied column addresses within a time period less than twice the minimum time interval. - View Dependent Claims (28)
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29. A method of operation in an integrated circuit memory device, the integrated circuit memory device having a storage array having storage cells arranged in plural rows and plural columns and a row decoder to select a row of storage cells within the storage array, the integrated circuit memory device further characterized by a minimum time interval comprising a minimum number of clock cycles must elapse between successive accesses to an open row of storage cells in the storage array, the method comprising:
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obtaining two or more externally supplied column addresses; opening a row of the storage array; selecting two or more columns in the open row in response to the respective externally supplied column addresses; and outputting read data associated with each of the selected two or more columns from the open row during a time period less than twice the minimum time interval. - View Dependent Claims (30, 31, 32)
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33. An integrated circuit memory device, comprising:
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a storage array having storage cells arranged in plural rows and plural columns; a row decoder to select a row of storage cells within the storage array; an interface to couple the integrated circuit memory device with an external interconnect; and circuitry to generate multiple column addresses for independently accessing portions of a selected row during a single column cycle time interval.
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Specification