Multi-phased computational reconfiguration

• US 20110154012A1
• Filed: 12/23/2009
• Published: 06/23/2011
• Est. Priority Date: 12/23/2009
• Status: Active Grant

• Current Assignee: L-3 Communications Integrated Systems LP (L3Harris Technologies, Inc.)
• Original Assignee: L-3 Communications Integrated Systems LP (L3Harris Technologies, Inc.)
• Inventors: Prasanna, Deepak, DeLaquil, Matthew P., Kusmanoff, Antone L.
• Granted Patent: US 8,397,054 B2
• Time in Patent Office: Days
• US Class Current: 713/100
• CPC Class Codes: G06F 2207/382 Reconfigurable for different fixed word lengths multigauge devices G06F2207/3828
• CPC Class Codes: G06F 2207/3884 Pipelining
• CPC Class Codes: G06F 7/00 Methods or arrangements for processing data by operating upon the order or content of the data handled logic circuits H03K19/00
• CPC Class Codes: G06F 7/5324 partitioned, i.e. using repetitively a smaller parallel parallel multiplier or using an array of such smaller multipliers

Abstract

Problem solution speed may be increased by dynamically changing processing device computational hardware configuration in concert with respective mathematical phases of an algorithm to match accuracy demands at various phases of computation. Smaller but faster hardware structures may be increased in size using real-time partial or full reconfiguration of a processing device to apply the smallest and fastest possible computational structure for the needed accuracy during each of multiple computational phases.

Claims

1. A method for dynamically reconfiguring a processing device, comprising:

providing a reconfigurable processing device, the processing device being at least partially reconfigurable from a first computational structure configured to process data with a first precision at a first computational speed to a second computational structure configured to process data with a second precision at a second computational speed, the second precision and second computational speed being different than the first precision and the first computational speed;

processing data with the first computational structure in a first computational phase to produce a first phase solution;

then dynamically reconfiguring at least a portion of the processing device from the first computational structure to the second computational structure; and

then processing data of the first phase solution with the second computational structure in a second computational phase to produce a second phase solution.

2. The method of claim 1, where the second precision is higher than the first precision and the first computational speed is faster than the second computational speed.

3. The method of claim 1, where the first and second phases are separate phases of an iterative mathematical algorithm, the second precision being higher than the first precision and the first computational speed being faster than the second computational speed.

4. The method of claim 1, further comprising processing data with the first computational structure in the first computational phase to produce the first phase solution having a first error level;

and then dynamically reconfiguring at least a portion of the processing device from the first computational structure to the second computational structure and processing data of the first phase solution with the second computational structure in the second computational phase to produce the second phase solution having a second error level, the first error level being greater than the second error level.

5. The method of claim 1, where the first and second phases are separate phases of an iterative mathematical algorithm;

and where the method further comprises processing data with the first computational structure in the first computational phase until the first phase solution has a first error level that meets a predefined minimum first error level threshold, and then dynamically reconfiguring at least a portion of the processing device from the first computational structure to the second computational structure and processing data of the first phase solution with the second computational structure in the second computational phase to produce the second phase solution having a second error level, the first error level being greater than the second error level; and

where the method further comprises terminating the first computational phase and dynamically reconfiguring at least a portion of the processing device to the second computational structure based on the first phase solution achieving the first error level that meets the predefined minimum first error level threshold.

6. The method of claim 1, further comprising prefiguring the second computational structure prior to the step of processing data with the first computational structure in a first computational phase to produce the first phase solution;

and then dynamically reconfiguring at least a portion of the processing device from the first computational structure to the prefigured second computational structure after processing data with the first computational structure in the first computational phase to produce the first phase solution.

7. The method of claim 1, where the first and second computational phases correspond to first and second phases of an mathematical algorithm that have different error level requirements.

8. The method of claim 1, where the processing device is at least partially reconfigurable from the second computational structure to a third computational structure configured to process data with a third precision at a third computational speed, the third precision being different than the first precision and second precision, and the third computational speed being different than the first computational speed and the second computational speed;

and where the method further comprises;

processing data with the first computational structure in a first computational phase to produce a first phase solution;

then dynamically reconfiguring at least a portion of the processing device from the first computational structure to the second computational structure;

then processing data of the first phase solution with the second computational structure in a second computational phase to produce a second phase solution;

then dynamically reconfiguring at least a portion of the processing device from the second computational structure to the third computational structure; and

then processing data of the second phase solution with the third computational structure in a third computational phase to produce a third phase solution.

9. The method of claim 1, where the reconfigurable processing device is a field programmable gate array (FPGA).

10. A system for dynamically reconfiguring a processing device, comprising:

a reconfigurable processing device configured with a first computational structure configured to process data with a first precision at a first computational speed, the processing device being at least partially reconfigurable from the first computational structure to a second computational structure configured to process data with a second precision at a second computational speed, the second precision and second computational speed being different than the first precision and the first computational speed; and

a computer processing system coupled by a datapath to the reconfigurable processing device, the computer processing system including memory and the second computational structure being prefigured in the memory of the computer processing system;

where the computer processing system is configured to dynamically reconfigure at least a portion of the processing device from the first computational structure to the second computational structure after data is processed with the first computational structure in a first computational phase to produce a first phase solution and before data of the first phase solution is processed with the second computational structure in a second computational phase to produce a second phase solution.

11. The system of claim 10, where the second precision is higher than the first precision and the first computational speed is faster than the second computational speed.

12. The system of claim 10, where the first and second phases are separate phases of an iterative mathematical algorithm, the second precision being higher than the first precision and the first computational speed being faster than the second computational speed.

13. The system of claim 10, where the first computational structure is configured to process data in the first computational phase to produce the first phase solution having a first error level;

where the second computational structure is configured to process data in the second computational phase to produce the second phase solution having a second error level, the first error level being greater than the second error level; and

where the computer processing system is configured to dynamically reconfigure at least a portion of the processing device from the first computational structure to the second computational structure after the first computational structure processes data in the first computational phase to produce the first phase solution and before the second computational structure processes the first phase solution data in the second computational phase to produce the second phase solution.

14. The system of claim 10, where the first and second phases are separate phases of an iterative mathematical algorithm;

where the first computational structure is configured to process data in the first computational phase to produce the first phase solution having a first error level and where the second computational structure is configured to process data in the second computational phase to produce the second phase solution having a second error level, the first error level being greater than the second error level; and

where the computer processing system is configured to terminate the first computational phase and dynamically reconfigure at least a portion of the processing device from the first computational structure to the second computational structure based on the first phase solution achieving a first error level that meets a predefined minimum first error level threshold.

15. The system of claim 10, where the first and second computational phases correspond to first and second phases of an mathematical algorithm that have different error level requirements.

16. The system of claim 10, where the processing device is at least partially reconfigurable from the second computational structure to a third computational structure configured to process data with a third precision at a third computational speed, the third precision being different than the first precision and second precision, and the third computational speed being different than the first computational speed and the second computational speed;

and where the computer processing system is configured to dynamically reconfigure at least a portion of the processing device from the second computational structure to the third computational structure after data is processed with the second computational structure in a second computational phase to produce a second phase solution and before data of the second phase solution is processed with the third computational structure in a third computational phase to produce a third phase solution.

17. The system of claim 10, where the reconfigurable processing device is a field programmable gate array (FPGA).

18. A method of for dynamically reconfiguring a processing device, comprising:

providing a reconfigurable processing device configured to execute a mathematical algorithm having multiple phases; and

dynamically changing the configuration of the reconfigurable processing device while executing the algorithm on the reconfigurable processing device from a first computational structure corresponding to the accuracy requirements of a first phase of the mathematical algorithm to a second computational structure corresponding to the accuracy requirements of a second phase of the mathematical algorithm.

19. The method of claim 18, where the mathematical algorithm is an iterative algorithm, where the accuracy requirements of the second phase of the mathematical algorithm is greater than the accuracy requirements of the first phase of the mathematical algorithm and where the method further comprises:

executing the first phase of the mathematical algorithm on the reconfigurable processing device using the first computational structure with a first precision at a first computational speed prior to dynamically changing the configuration of the reconfigurable processing device; and

initiating the second mathematical algorithm phase starting with data produced during the first mathematical algorithm phase, and executing the second phase of the mathematical algorithm on the reconfigurable processing device using the second computational structure with a second precision at a second computational speed after dynamically changing the configuration of the reconfigurable processing device, the second precision being higher than the first precision and the first computational speed being faster than the second computational speed.

20. The method of claim 19, where the method further comprises executing the first phase of the mathematical algorithm on the reconfigurable processing device using the first computational structure until the first phase solution has a first error level that meets a predefined minimum first error level threshold, and then dynamically reconfiguring at least a portion of the processing device from the first computational structure to the second computational structure and initiating the second mathematical algorithm phase starting with data produced during the first mathematical algorithm phase to produce the second phase solution having a second error level, the first error level being greater than the second error level;

and where the method further comprises terminating the first phase of the mathematical algorithm and dynamically reconfiguring at least a portion of the processing device to the second computational structure based on the first phase solution achieving the first error level that meets the predefined minimum first error level threshold.

21. The method of claim 18, where the reconfigurable processing device is a field programmable gate array (FPGA).

22. The method of claim 18, where the reconfigurable processing device is configured to execute any mathematical algorithm having an arbitrary number of multiple phases;

and where the method further comprises dynamically changing the configuration of the reconfigurable processing device while executing the algorithm on the reconfigurable processing device from a given computational structure corresponding to the accuracy requirements of all but the last of the arbitrary number of phases of the mathematical algorithm to another computational structure corresponding to the accuracy requirements of another successive phase of the mathematical algorithm.