COMPACT ELECTRICAL SWITCHING DEVICES WITH NANOTUBE ELEMENTS, AND METHODS OF MAKING SAME

• US 20110156009A1
• Filed: 12/31/2009
• Published: 06/30/2011
• Est. Priority Date: 12/31/2009
• Status: Active Grant

• Current Assignee: Nantero Incorporated
• Original Assignee: Nantero Incorporated
• Inventors: Bertin, Claude L., Manning, H. Montgomery, Rueckes, Thomas
• Granted Patent: US 8,222,704 B2
• Time in Patent Office: Days
• US Class Current: 257/40
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 13/025 using fullerenes, e.g. C60, or nanotubes, e.g. carbon or silicon nanotubes
• CPC Class Codes: H01L 29/0665 the shape of the body defining a nanostructure nanotechnology per se B82B
• CPC Class Codes: H01L 29/43 characterised by the materials of which they are formed
• CPC Class Codes: H10B 63/00 Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
• CPC Class Codes: H10K 85/221 Carbon nanotubes
• CPC Class Codes: Y10S 977/742 Carbon nanotubes, CNTs
• CPC Class Codes: Y10S 977/936 in a transistor or 3-terminal device

Abstract

An electrical device includes a substrate; first and second active areas; first and second word lines disposed in a first plane; first and second bit lines in a second plane and in electrical communication with first and second active areas; and a reference line disposed in a third plane. A nanotube element disposed in a fourth plane is in electrical communication with first and second active areas and the reference line via electrical connections at a first surface of the nanotube element. The nanotube element includes first and second regions having resistance states that are independently adjustable in response to electrical stimuli, wherein the first and second regions nonvolatilely retain the resistance states. Arrays of such electrical devices can be formed as nonvolatile memory devices. Methods for fabricating such devices are also disclosed.

Claims

1. An electrical device, comprising:

a substrate having an upper surface;

a first active area in the substrate;

a second active area in the substrate;

a first word line and a second word line disposed in a first plane positioned above the upper surface of the substrate;

a first bit line in electrical communication with the first active area, and a second bit line in electrical communication with the second active area, the first and second bit lines disposed in a second plane positioned above the first plane;

a first reference line disposed in a third plane positioned above the first plane; and

a first nanotube element disposed in a fourth plane positioned above the first and second planes, the first nanotube element having a first surface and extending laterally in the fourth plane parallel to a plane of the substrate,

the first nanotube element being in electrical communication with the first active region, the second active region and the first reference line via electrical contacts at the first surface of the first nanotube element,

the first nanotube element comprising a first region and a second region, the first and second regions having resistance states that are independently adjustable in response to electrical stimuli, the first and second regions nonvolatilely retaining said resistance states.

2. The device of claim 1, wherein:

a resistance state of a first region of the first nanotube element is independently adjustable responsive to electrical stimulus on the first word line and at least one of the first bit line and the first reference line, the first region nonvolatilely retaining the first resistance state, and

a resistance state of a second region of the first nanotube element is independently adjustable responsive to electrical stimulus on the second word line and at least one of the second bit line and the first reference line, the second region nonvolatilely retaining the second resistance state.

3. The device of claim 1, wherein:

the first active area comprises a first source region, a first drain region, and a first channel region disposed between the first source region and the first drain region;

the second active area comprises a second source region, a second drain region, and a second channel region disposed between the second source region and the second drain region;

the first word line is disposed over the first channel region, and the second word line is disposed over the second channel region; and

the first bit line is in electrical communication with the first drain region, and the second bit line is in electrical communication with the second drain region.

4. The device of claim 3, further comprising:

a third active area in the substrate, the third active area comprising a third source region, the first drain region, and a third channel region disposed between the third source region and the first drain region;

a fourth active area in the substrate, the fourth active area comprising a fourth source region, the second drain region, and a fourth channel region disposed between the fourth source region and the second drain region;

a third word line disposed over the third channel region, and a fourth word line disposed over the fourth channel region, the third and fourth word lines being disposed in the first plane;

second and third reference lines disposed in the third plane;

a second nanotube element in electrical communication with the third source region and the second reference line, a resistance state of the second nanotube element being independently adjustable responsive to electrical stimulus on the third word line and at least one of the first bit line and the second reference line; and

a third nanotube element in electrical communication with the fourth source region and the third reference line, a resistance state of the third nanotube element being independently adjustable responsive to electrical stimulus on the fourth word line and at least one of the second bit line and the third reference line.

5. The device of claim 2, wherein the resistance states of the first and second regions of the nanotube element are each independently adjustable between a low resistance state and a high resistance state, the low resistance state corresponding to a digital “

1”

state and the high resistance state corresponding to a digital “

0”

state.

6. The device of claim 2, wherein the resistance states of the first and second regions of the nanotube element are each independently adjustable between a low resistance state, a high resistance state, and at least one intermediate resistance state.

7. The device of claim 1, wherein the third plane is positioned above the fourth plane.

8. The device of claim 1, wherein third plane is positioned between the second and fourth planes.

9. The device of claim 1, wherein the first and second word lines are arranged parallel to the reference line.

10. The device of claim 1, wherein at least a portion of each of first and second bit lines is arranged at an obtuse angle relative to the first and second word lines.

11. The device of claim 10, wherein the first and second channel regions are arranged at an acute angle relative to the first and second word lines.

12. The device of claim 11, wherein the obtuse angle is about 104°

, and wherein the acute angle is about 76°

.

13. The device of claim 11, wherein at least a portion of the first nanotube element is arranged at the obtuse angle relative to the first and second word lines.

14. The device of claim 13, wherein the first nanotube element is laterally offset relative to the first and second bit lines.

15. The device of claim 1, wherein the first nanotube element forms a trace extending substantially parallel to the first and second bit lines.

16. The device of claim 1, wherein the first nanotube element extends over the first and second active areas, the first and second word lines, and the first and second bit lines.

17. The device of claim 1, further comprising peripheral circuitry for applying electrical stimulus to the first and second word lines, the first and second bit lines, and the reference line.

18. The device of claim 1, further comprising a passivation layer disposed on the nanotube element, the passivation layer having a gap defined therein, the gap being adjacent to the nanotube element.

19. The device of claim 1, wherein the first nanotube element comprises substantially a monolayer of nanotubes.

20. The device of claim 2, wherein a current path through the first region of the first nanotube element extends laterally in the fourth plane, and wherein a current path through the second region of the first nanotube element extends laterally in the fourth plane.

21. The device of claim 2, wherein the first region extends laterally between a conductive stud in contact with the first drain region and the reference line, and wherein the second region extends laterally between a conductive stud in contact with the second drain region and the reference line.

22. An array of electrical devices, comprising:

a substrate having an upper surface;

a plurality of active areas in the substrate;

a plurality of word lines disposed in a first plane positioned above the upper surface of the substrate;

a plurality of bit lines disposed in a second plane positioned above the first plane, each bit line in electrical communication with one of the active areas;

a plurality of reference lines disposed in a third plane positioned above the first plane; and

at least one nanotube element disposed in a fourth plane positioned above the first and second planes, the at least one nanotube element having a plurality of nanotube regions, each nanotube region in electrical communication with an active area and a reference line via electrical contacts at a first surface of the first nanotube element, the plurality of nanotube regions having resistance states that are independently adjustable in response to electrical stimuli,

wherein each nanotube region shares a reference line with an adjacent nanotube region, and

wherein each nanotube region shares a bit line with an adjacent nanotube region.

23. A method of making an electrical device, the method comprising:

providing a substrate;

forming first and second active areas in the substrate;

forming a first word line and a second word line in a first plane positioned above the upper surface of the substrate;

forming first and second bit lines in a second plane positioned above the first plane;

forming a first reference line in a third plane positioned above the upper surface of the substrate;

forming a first nanotube element in a fourth plane positioned above the first and second planes, the first nanotube element having a first surface and extending laterally in the fourth plane parallel to a plane of the substrate; and

forming electrical connections between the first bit line and the first active area, between the second bit line and the second active area, between the first nanotube element and the first reference line, between the first nanotube element and the first active region, and between the first nanotube element and the second active region, such that the first nanotube element is in electrical communication with the first active region, the second active region and the first reference line via electrical contacts at the first surface of the first nanotube element.

24. The method of claim 23, wherein the first active area comprises a first source region, a first drain region, and a first channel region disposed between the first source region and the first drain region, and the second active area comprises a second source region, a second drain region, and a second channel region disposed between the second source region and the second drain region, the method comprising forming the first word line over the first channel region, and forming the second word line over the second channel region.

25. The method of claim 24, further comprising:

forming third and fourth active areas in the substrate, the third active area comprising a third source region, the first drain region, and a third channel region disposed between the third source region and the first drain region, the fourth active area comprising a fourth source region, the second drain region, and a fourth channel region disposed between the fourth source region and the second drain region;

forming a third word line over the third channel region, and forming a fourth word line over the fourth channel region, the third and fourth word lines being disposed in the first plane;

forming second and third reference lines disposed in the third plane;

forming second and third nanotube elements disposed in the fourth plane; and

forming electrical connections between the second nanotube element and the third source region, between the second nanotube element and the second reference line, between the third nanotube element and the fourth source region, and between the third nanotube element and the third reference line.