Transistor

• US 20110156020A1
• Filed: 06/11/2010
• Published: 06/30/2011
• Est. Priority Date: 12/24/2009
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Song, I-hun, Park, Sung-ho, Kim, Chang-jung, Jeon, Sang-hun
• Application Number:
  US12/801,501
• Publication Number:
  US 20110156020A1
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 2013/0073 Write using bi-directional cell biasing
• CPC Class Codes: G11C 2213/31 Material having complex metal oxide, e.g. perovskite structure
• CPC Class Codes: G11C 2213/32 Material having simple binary metal oxide structure
• CPC Class Codes: G11C 2213/72 Array wherein the access device being a diode
• CPC Class Codes: G11C 2213/73 Array where access device function, e.g. diode function, being merged with memorizing function of memory element
• CPC Class Codes: G11C 2213/74 Array wherein each memory cell has more than one access device
• CPC Class Codes: G11C 2213/76 Array using an access device for each cell which being not a transistor and not a diode
• CPC Class Codes: H10B 63/20 comprising selection components having two electrodes, e.g. diodes
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8833 Binary metal oxides, e.g. TaOx
• CPC Class Codes: H10N 70/8836 Complex metal oxides, e.g. perovskites, spinels

Abstract

Provided is a transistor including a semiconductor insertion layer between a channel layer and a source electrode. A potential barrier between the channel layer and the source electrode may be increased by the semiconductor insertion layer. The channel layer may be an oxide semiconductor layer. The transistor may be an enhancement mode transistor.

Claims

1. A transistor comprising:

a channel layer including an oxide semiconductor;

a gate electrode corresponding to the channel layer;

a source electrode and a drain electrode contacting portions of the channel layer; and

a semiconductor insertion layer between the channel layer and the source electrode,

wherein a potential barrier between the channel layer and the source electrode is increased by the semiconductor insertion layer.

2. The transistor of claim 1, wherein the channel layer is an n-type channel layer, and a work function of the semiconductor insertion layer is greater than that of the channel layer.

3. The transistor of claim 2, wherein an n-type carrier concentration of the semiconductor insertion layer is lower than that of the channel layer.

4. The transistor of claim 1, wherein the channel layer is a p-type channel layer, and a work function of the semiconductor insertion layer is smaller than that of the channel layer.

5. The transistor of claim 4, wherein a p-type carrier concentration of the semiconductor insertion layer is lower than that of the channel layer.

6. The transistor of claim 1, wherein the channel layer includes any one selected from the group consisting of ZnO, GaO, InO, SnO, CdO, CaO, AlO, TiO, TaO, NbO, LnO, HfO, ZrO, YO, NiO, CuO, and a combination thereof, or oxide semiconductors thereof.

7. The transistor of claim 6, wherein the channel layer is formed of a ZnO-based oxide semiconductor.

8. The transistor of claim 7, wherein the ZnO-based oxide semiconductor further includes at least one selected from the group consisting of In, Ga, Sn, Ti, Zr, Hf, Y, and Ta.

9. The transistor of claim 1, wherein the semiconductor insertion layer includes one selected from the group consisting of SiC, AlN, GaN, InN, AlP, GaP, InAs, GaAs, AlAs, InSb, GaSb, ZnS, CdS, ZnTe, CdTe, CdSe, CdS, ZnO, GaO, InO, SnO, CdO, CaO, AlO, TiO, TaO, NbO, LnO, HfO, ZrO, YO, NiO, CuO, and a combination thereof, or compounds thereof.

10. The transistor of claim 1, wherein the semiconductor insertion layer has an energy bandgap of about 0.5 to about 4.0 eV.

11. The transistor of claim 1, wherein the semiconductor insertion layer has a thickness of about 1 to about 300 Å

.

12. The transistor of claim 1, wherein the transistor is an enhancement mode transistor.

13. The transistor of claim 1, wherein the semiconductor insertion layer is a first semiconductor insertion layer, further comprising:

a second semiconductor insertion layer between the channel layer and the drain electrode.

14. The transistor of claim 13, wherein the first and second semiconductor insertion layers are formed of the same material.

15. The transistor of claim 1, wherein the transistor is a thin film transistor (TFT) having a top-gate structure.

16. The transistor of claim 1, wherein the transistor is a TFT having a bottom-gate structure.

17. The transistor of claim 1, further comprising:

a gate insulating layer between the channel layer and the gate electrode.

18. The transistor of claim 17, wherein the gate insulating layer includes one selected from the group consisting of a silicon oxide layer, a silicon nitride layer, and a high-dielectric material layer having a dielectric constant greater than that of the silicon nitride layer.

19. The transistor of claim 18, wherein the gate insulating layer has a structure including at least two stacked layers from among the silicon oxide layer, the silicon nitride layer, and the high-dielectric material layer.