SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

• US 20110156022A1
• Filed: 12/21/2010
• Published: 06/30/2011
• Est. Priority Date: 12/25/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: GODO, Hiromichi, YAMAZAKI, Shunpei, KAWAE, Daisuke
• Granted Patent: US 8,664,652 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A semiconductor device which includes an oxide semiconductor layer, a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, a gate insulating layer covering the oxide semiconductor layer, the source electrode, and the drain electrode, and a gate electrode over the gate insulating layer is provided. The thickness of the oxide semiconductor layer is greater than or equal to 1 nm and less than or equal to 10 nm. The gate insulating layer satisfies a relation where ε_r/d is greater than or equal to 0.08 (nm⁻¹) and less than or equal to 7.9 (nm⁻¹) when the relative permittivity of a material used for the gate insulating layer is ε_r and the thickness of the gate insulating layer is d. The distance between the source electrode and the drain electrode is greater than or equal to 10 nm and less than or equal to 1 μm.

Claims

1. A semiconductor device comprising:

an oxide semiconductor layer;

a source electrode and a drain electrode electrically connected to the oxide semiconductor layer;

a gate insulating layer covering the oxide semiconductor layer, the source electrode, and the drain electrode; and

a gate electrode over the gate insulating layer,

wherein a thickness of the oxide semiconductor layer is greater than or equal to 1 nm and less than or equal to 10 nm,

wherein the gate insulating layer satisfies a relation where ε

_r/d is greater than or equal to 0.08 (nm<sup>−

1</sup>) and less than or equal to 7.9 (nm<sup>−

1</sup>) when a relative permittivity of a material used for the gate insulating layer is ε

_r and a thickness of the gate insulating layer is d, and

wherein a distance between the source electrode and the drain electrode is greater than or equal to 10 nm and less than or equal to 1 μ

m.

2. The semiconductor device according to claim 1, further comprising insulating layers over the source electrode and the drain electrode.

3. The semiconductor device according to claim 1, wherein an off current density between the source electrode and the drain electrode is 100 zA/μ

m or less.

4. The semiconductor device according to claim 1, wherein the semiconductor device is provided over a surface having an arithmetic mean deviation of 1 nm or less.

5. A semiconductor device comprising:

an oxide semiconductor layer;

a source electrode and a drain electrode electrically connected to the oxide semiconductor layer;

a gate insulating layer covering the oxide semiconductor layer, the source electrode, and the drain electrode; and

a gate electrode over the gate insulating layer,

wherein a thickness of the oxide semiconductor layer is greater than or equal to 1 nm and less than or equal to 10 nm,

wherein the gate insulating layer satisfies a relation where ε

_r/d is greater than or equal to 0.08 (nm<sup>−

1</sup>) and less than or equal to 7.9 (nm<sup>−

1</sup>) when a relative permittivity of a material used for the gate insulating layer is ε

_r and a thickness of the gate insulating layer is d,

wherein a distance between the source electrode and the drain electrode is greater than or equal to 10 nm and less than or equal to 1 μ

m, and

wherein each side surface of the source electrode and the drain electrode has an oxide region.

6. The semiconductor device according to claim 5, further comprising insulating layers over the source electrode and the drain electrode.

7. The semiconductor device according to claim 5, wherein an off current density between the source electrode and the drain electrode is 100 zA/μ

m or less.

8. The semiconductor device according to claim 5, wherein the semiconductor device is provided over a surface having an arithmetic mean deviation of 1 nm or less.

9. A method for manufacturing a semiconductor device, comprising the steps of:

forming an oxide semiconductor layer over a substrate;

forming a source electrode and a drain electrode electrically connected to the oxide semiconductor layer;

oxidizing side surfaces of the source electrode and the drain electrode;

forming a gate insulating layer covering the oxide semiconductor layer, the source electrode, and the drain electrode; and

forming a gate electrode over the gate insulating layer.

10. The method for manufacturing a semiconductor device according to claim 9, wherein the side surfaces of the source electrode and the drain electrode are oxidized by plasma treatment with a high frequency power of greater than or equal to 300 MHz and less than or equal to 300 GHz and a mixed gas of oxygen and argon.

11. The method for manufacturing a semiconductor device according to claim 10, wherein the oxide semiconductor layer is supplied with oxygen by the plasma treatment.

12. The method for manufacturing a semiconductor device according to claim 10, wherein a process for reducing hydrogen in the oxide semiconductor layer is performed before the plasma treatment.

13. The method for manufacturing a semiconductor device according to claim 9,

wherein a thickness of the oxide semiconductor layer is greater than or equal to 1 nm and less than or equal to 10 nm,

wherein the gate insulating layer satisfies a relation where ε

_r/d is greater than or equal to 0.08 (nm<sup>−

1</sup>) and less than or equal to 7.9 (nm<sup>−

1</sup>) when a relative permittivity of a material used for the gate insulating layer is ε

_r and a thickness of the gate insulating layer is d, and

wherein a distance between the source electrode and the drain electrode is greater than or equal to 10 nm and less than or equal to 1 μ

m.

14. The method for manufacturing a semiconductor device according to claim 9, wherein a substrate whose surface has an arithmetic mean deviation of 1 nm or less is used as the substrate.

15. A method for manufacturing a semiconductor device, comprising the steps of:

forming an oxide semiconductor layer over a substrate;

forming a source electrode and a drain electrode electrically connected to the oxide semiconductor layer;

forming a first insulating layer over the source electrode, and a second insulating layer over the drain electrode;

oxidizing side surfaces of the source electrode and the drain electrode;

forming a gate insulating layer covering the oxide semiconductor layer, the source electrode, and the drain electrode; and

forming a gate electrode over the gate insulating layer.

16. The method for manufacturing a semiconductor device according to claim 15, wherein the side surfaces of the source electrode and the drain electrode are oxidized by plasma treatment with a high frequency power of greater than or equal to 300 MHz and less than or equal to 300 GHz and a mixed gas of oxygen and argon.

17. The method for manufacturing a semiconductor device according to claim 16, wherein the oxide semiconductor layer is supplied with oxygen by the plasma treatment.

18. The method for manufacturing a semiconductor device according to claim 17, wherein a process for reducing hydrogen in the oxide semiconductor layer is performed before the plasma treatment.

19. The method for manufacturing a semiconductor device according to claim 15,

wherein a thickness of the oxide semiconductor layer is greater than or equal to 1 nm and less than or equal to 10 nm,

wherein the gate insulating layer satisfies a relation where ε

_r/d is greater than or equal to 0.08 (nm<sup>−

1</sup>) and less than or equal to 7.9 (nm<sup>−

1</sup>) when a relative permittivity of a material used for the gate insulating layer is ε

_r and a thickness of the gate insulating layer is d, and

wherein a distance between the source electrode and the drain electrode is greater than or equal to 10 nm and less than or equal to 1 μ

m.

20. The method for manufacturing a semiconductor device according to claim 15, wherein a substrate whose surface has an arithmetic mean deviation of 1 nm or less is used as the substrate.