MEMORY DEVICE, SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE
First Claim
1. A memory device comprising a plurality of memory elements, the memory elements each comprising:
- a first phase-inversion element and a second phase-inversion element which hold data by being connected to each other such that an input terminal of the first phase-inversion element is connected to an output terminal of the second phase-inversion element and an input terminal of the second phase-inversion element is connected to an output terminal of the first phase-inversion element;
a capacitor; and
a transistor which includes an oxide semiconductor in a channel formation region and which is configured to control writing of the data to the capacitor.
1 Assignment
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Accused Products
Abstract
An object is to provide a memory device which does not need a complex manufacturing process and whose power consumption can be suppressed, and a semiconductor device including the memory device. A solution is to provide a capacitor which holds data and a switching element which controls storing and releasing charge in the capacitor in a memory element. In the memory element, a phase-inversion element such as an inverter or a clocked inverter includes the phase of an input signal is inverted and the signal is output. For the switching element, a transistor including an oxide semiconductor in a channel formation region is used. In the case where application of a power supply voltage to the phase-inversion element is stopped, the data is stored in the capacitor, so that the data is held in the capacitor even when the application of the power supply voltage to the phase-inversion element is stopped.
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Citations
15 Claims
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1. A memory device comprising a plurality of memory elements, the memory elements each comprising:
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a first phase-inversion element and a second phase-inversion element which hold data by being connected to each other such that an input terminal of the first phase-inversion element is connected to an output terminal of the second phase-inversion element and an input terminal of the second phase-inversion element is connected to an output terminal of the first phase-inversion element; a capacitor; and a transistor which includes an oxide semiconductor in a channel formation region and which is configured to control writing of the data to the capacitor. - View Dependent Claims (6, 10, 11, 12, 13, 14)
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2. A memory device comprising a plurality of memory elements, the memory elements each comprising:
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a first phase-inversion element; a second phase-inversion element an input terminal of which is connected to an output terminal of the first phase-inversion element; a first switching element which is configured to control input of a signal including data to an input terminal of the first phase-inversion element; a second switching element which is configured to control connection between the input terminal of the first phase-inversion element and an output terminal of the second phase-inversion element; a capacitor; and a transistor which includes an oxide semiconductor in a channel formation region and which is configured to control writing of the data to the capacitor.
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3. A memory device comprising a plurality of memory elements, the memory elements each comprising:
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a first phase-inversion element; a second phase-inversion element an input terminal of which is connected to an output terminal of the first phase-inversion element; a first switching element which is configured to control input of a signal including data to an input terminal of the first phase-inversion element; a second switching element which is configured to control connection between the input terminal of the first phase-inversion element and an output terminal of the second phase-inversion element; a capacitor; and a transistor which includes an oxide semiconductor in a channel formation region and which is configured to control connection between the input terminal of the first phase-inversion element and the capacitor.
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4. A memory device comprising a plurality of memory elements, the memory elements each comprising:
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a first phase-inversion element; a second phase-inversion element an input terminal of which is connected to an output terminal of the first phase-inversion element; a first switching element which is configured to control input of a signal including data to an input terminal of the first phase-inversion element; a second switching element which is configured to control connection between the input terminal of the first phase-inversion element and an output terminal of the second phase-inversion element; a third switching element which is configured to control output of a potential of the output terminal of the first phase-inversion element; a capacitor; a transistor which includes an oxide semiconductor in a channel formation region and which is configured to control writing of the data to the capacitor; a third phase-inversion element an input terminal of which is supplied with a potential including the data written in the capacitor; and a fourth switching element which is configured to control output of a potential of an output terminal of the third phase-inversion element. - View Dependent Claims (15)
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5. A memory device comprising a plurality of memory elements, the memory elements each comprising:
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a first phase-inversion element; a second phase-inversion element an input terminal of which is connected to an output terminal of the first phase-inversion element; a first switching element which is configured to control connection between an input terminal of the first phase-inversion element and a node to which a signal including data is input; a second switching element which is configured to control connection between the input terminal of the first phase-inversion element and an output terminal of the second phase-inversion element; a third switching element which is configured to control output of a potential of the output terminal of the first phase-inversion element; a capacitor; a transistor which includes an oxide semiconductor in a channel formation region and which is configured to control connection between the node and the capacitor; a third phase-inversion element an input terminal of which is supplied with a potential including the data written in the capacitor; and a fourth switching element which is configured to control output of a potential of an output terminal of the third phase-inversion element.
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7. A memory device comprising a plurality of memory elements, the memory elements each comprising:
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a first phase-inversion element; a second phase-inversion element an input terminal of which is connected to an output terminal of the first phase-inversion element; a first switching element which is configured to control input of a signal including data to an input terminal of the first phase-inversion element; a second switching element which is configured to control connection between the input terminal of the first phase-inversion element and an output terminal of the second phase-inversion element; a first capacitor; a first transistor which includes an oxide semiconductor in a channel formation region and which is configured to control writing of the data to the first capacitor; a second capacitor; and a second transistor which includes an oxide semiconductor in a channel formation region and which is configured to control writing of the data to the second capacitor. - View Dependent Claims (9)
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8. A memory device comprising a plurality of memory elements, the memory elements each comprising:
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a first phase-inversion element; a second phase-inversion element an input terminal of which is connected to an output terminal of the first phase-inversion element; a first switching element which is configured to control input of a signal including data to an input terminal of the first phase-inversion element; a second switching element which is configured to control connection between the input terminal of the first phase-inversion element and an output terminal of the second phase-inversion element; a first capacitor; a first transistor which includes an oxide semiconductor in a channel formation region and which is configured to control connection between the input terminal of the first phase-inversion element and the first capacitor; a second capacitor; and a second transistor which includes an oxide semiconductor in a channel formation region and which is configured to control connection between the output terminal of the first phase-inversion element and the second capacitor.
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Specification