MEMORY DEVICE AND SEMICONDUCTOR DEVICE

• US 20110156025A1
• Filed: 12/22/2010
• Published: 06/30/2011
• Est. Priority Date: 12/28/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: MIYAKE, Hiroyuki, SHIONOIRI, Yutaka, KATO, Kiyoshi
• Granted Patent: US 9,472,559 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1251 comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/13 combined with thin-film or thick-film passive components
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

It is an object to provide a memory device whose power consumption can be suppressed and a semiconductor device including the memory device. As a switching element for holding electric charge accumulated in a transistor which functions as a memory element, a transistor including an oxide semiconductor film as an active layer is provided for each memory cell in the memory device. The transistor which is used as a memory element has a first gate electrode, a second gate electrode, a semiconductor film located between the first gate electrode and the second gate electrode, a first insulating film located between the first gate electrode and the semiconductor film, a second insulating film located between the second gate electrode and the semiconductor film, and a source electrode and a drain electrode in contact with the semiconductor film.

Claims

1. A semiconductor device comprising:

a first line;

a second line;

a third line;

a fourth line; and

a memory cell comprising a first transistor and a second transistor,

wherein the first transistor comprises;

a first gate electrode;

a first insulating film over the first gate electrode;

a first semiconductor film over the first insulating film;

a first source electrode in electrical contact with the first semiconductor film;

a first drain electrode in electrical contact with the first semiconductor film;

a second insulating film over the first semiconductor film, the first source electrode, and the first drain electrode; and

a second gate electrode over the second insulating film,

wherein the second transistor comprises;

a third gate electrode;

a third insulating film over the third gate electrode;

a second semiconductor film over the third insulating film;

a fourth insulating film over the second semiconductor film;

a second source electrode in electrical contact with the second semiconductor film; and

a second drain electrode in electrical contact with the second semiconductor film,

wherein the first gate electrode of the first transistor is electrically connected to the first line,

wherein the third gate electrode of the second transistor is electrically connected to the second line,

wherein one of a source and a drain of the first transistor is electrically connected to the third line,

wherein one of a source and a drain of the second transistor is electrically connected to the fourth line,

wherein the other of the source and the drain of the second transistor is electrically connected to the second gate electrode of the first transistor, and

wherein the second semiconductor film includes an oxide semiconductor.

2. The semiconductor device according to claim 1, wherein the oxide semiconductor is an In—

Ga—

Zn—

O-based oxide semiconductor.

3. The semiconductor device according to claim 1, wherein hydrogen concentration of the oxide semiconductor is 5×

10¹⁹/cm³ or less.

4. The semiconductor device according to claim 1, wherein off-state current density of the second transistor is 100 zA/μ

m or less.

5. The semiconductor device according to claim 1, wherein the second insulating film is located over the first source electrode and the first drain electrode.

6. A semiconductor device comprising:

a first line;

a second line;

a third line;

a fourth line; and

a memory cell comprising a first transistor and a second transistor,

wherein the first transistor comprises;

a first gate electrode;

a first insulating film over the first gate electrode;

a first semiconductor film over the first insulating film;

a first source electrode in electrical contact with the first semiconductor film;

a first drain electrode in electrical contact with the first semiconductor film;

a second insulating film over the first semiconductor film, the first source electrode, and the first drain electrode; and

a second gate electrode over the second insulating film,

wherein the second transistor comprises;

a third gate electrode;

a third insulating film over the third gate electrode;

a second semiconductor film over the third insulating film;

a fourth insulating film over the second semiconductor film;

a second source electrode in electrical contact with the second semiconductor film; and

a second drain electrode in electrical contact with the second semiconductor film,

wherein the first gate electrode of the first transistor is electrically connected to the first line,

wherein the third gate electrode of the second transistor is electrically connected to the second line,

wherein one of a source and a drain of the first transistor is electrically connected to the third line,

wherein one of a source and a drain of the second transistor is electrically connected to the fourth line,

wherein the other of the source and the drain of the second transistor is electrically connected to the second gate electrode of the first transistor, and

wherein the first semiconductor film and the second semiconductor film include an oxide semiconductor.

7. The semiconductor device according to claim 6, wherein the oxide semiconductor is an In—

Ga—

Zn—

O-based oxide semiconductor.

8. The semiconductor device according to claim 6, wherein hydrogen concentration of the oxide semiconductor is 5×

10¹⁹/cm³ or less.

9. The semiconductor device according to claim 6, wherein off-state current density of the second transistor is 100 zA/μ

m or less.

10. The semiconductor device according to claim 6, wherein the second insulating film is located over the first source electrode and the first drain electrode.

11. A semiconductor device comprising:

a first line;

a second line;

a third line;

a fourth line; and

a memory cell comprising a first transistor and a second transistor,

wherein the first transistor comprises;

a first gate electrode;

a first insulating film over the first gate electrode;

a first semiconductor film over the first insulating film;

a first source electrode in electrical contact with the first semiconductor film;

a first drain electrode in electrical contact with the first semiconductor film;

a second insulating film over the first semiconductor film, the first source electrode, and the first drain electrode; and

a second gate electrode over the second insulating film,

wherein the second transistor comprises;

a third gate electrode;

a third insulating film over the third gate electrode;

a second semiconductor film over the third insulating film;

a fourth insulating film over the second semiconductor film;

a second source electrode in electrical contact with the second semiconductor film; and

a second drain electrode in electrical contact with the second semiconductor film,

wherein the first gate electrode of the first transistor is electrically connected to the first line,

wherein the third gate electrode of the second transistor is electrically connected to the second line,

wherein one of a source and a drain of the first transistor is electrically connected to the third line,

wherein one of a source and a drain of the second transistor is electrically connected to the fourth line,

wherein the other of the source and the drain of the second transistor is electrically connected to the second gate electrode of the first transistor,

wherein the second semiconductor film includes an oxide semiconductor, and

wherein one of the first source electrode and the first drain electrode overlaps with the second gate electrode with the second insulating film therebetween.

12. The semiconductor device according to claim 11, wherein the oxide semiconductor is an In—

Ga—

Zn—

O-based oxide semiconductor.

13. The semiconductor device according to claim 11, wherein hydrogen concentration of the oxide semiconductor is 5×

10¹⁹/cm³ or less.

14. The semiconductor device according to claim 11, wherein off-state current density of the second transistor is 100 zA/μ

m or less.

15. The semiconductor device according to claim 11, wherein the second insulating film is located over the first source electrode and the first drain electrode.

16. A semiconductor device comprising:

a first line;

a second line;

a third line;

a fourth line; and

a memory cell comprising a first transistor and a second transistor,

wherein the first transistor comprises;

a first gate electrode;

a first insulating film over the first gate electrode;

a first semiconductor film over the first insulating film;

a first source electrode in electrical contact with the first semiconductor film;

a first drain electrode in electrical contact with the first semiconductor film;

a second insulating film over the first semiconductor film, the first source electrode, and the first drain electrode; and

a second gate electrode over the second insulating film,

wherein the second transistor comprises;

a third gate electrode;

a third insulating film over the third gate electrode;

a second semiconductor film over the third insulating film;

a fourth insulating film over the second semiconductor film;

a second source electrode in electrical contact with the second semiconductor film; and

a second drain electrode in electrical contact with the second semiconductor film,

wherein the first gate electrode of the first transistor is electrically connected to the first line,

wherein the third gate electrode of the second transistor is electrically connected to the second line,

wherein one of a source and a drain of the first transistor is electrically connected to the third line,

wherein one of a source and a drain of the second transistor is electrically connected to the fourth line,

wherein the other of the source and the drain of the second transistor is electrically connected to the second gate electrode of the first transistor,

wherein the first semiconductor film and the second semiconductor film include an oxide semiconductor, and

wherein one of the first source electrode and the first drain electrode overlaps with the second gate electrode with the second insulating film therebetween.

17. The semiconductor device according to claim 16, wherein the oxide semiconductor is an In—

Ga—

Zn—

O-based oxide semiconductor.

18. The semiconductor device according to claim 16, wherein hydrogen concentration of the oxide semiconductor is 5×

10¹⁹/cm³ or less.

19. The semiconductor device according to claim 16, wherein off-state current density of the second transistor is 100 zA/μ

m or less.

20. The semiconductor device according to claim 16, wherein the second insulating film is located over the first source electrode and the first drain electrode.

21. A semiconductor device comprising a plurality of memory cells,

wherein each of the plurality of memory cells includes a first transistor and a second transistor,

wherein the first transistor comprises:

a first gate electrode;

a second gate electrode over the first gate electrode; and

a first channel formation region between the first gate electrode and the second gate electrode,

wherein the second transistor comprises a second channel formation region including an oxide semiconductor, and

wherein one of a first terminal and a second terminal of the second transistor is electrically connected to the second gate electrode of the first transistor.

22. The semiconductor device according to claim 21, wherein the oxide semiconductor is an In—

Ga—

Zn—

O-based oxide semiconductor.

23. The semiconductor device according to claim 21, wherein hydrogen concentration of the oxide semiconductor is 5×

10¹⁹/cm³ or less.

24. The semiconductor device according to claim 21, wherein off-state current density of the second transistor is 100 zA/μ

m or less.