SEMICONDUCTOR DEVICE

• US 20110156027A1
• Filed: 12/22/2010
• Published: 06/30/2011
• Est. Priority Date: 12/25/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kato, Kiyoshi, Koyama, Jun, Yamazaki, Shunpei
• Granted Patent: US 8,455,868 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

An object of one embodiment of the present invention is to provide a semiconductor device with a novel structure in which stored data can be stored even when power is not supplied in a data storing time and there is no limitation on the number of times of writing. The semiconductor device includes a first transistor which includes a first channel formation region using a semiconductor material other than an oxide semiconductor, a second transistor which includes a second channel formation region using an oxide semiconductor material, and a capacitor. One of a second source electrode and a second drain electrode of the second transistor is electrically connected to one electrode of the capacitor.

Claims

1. A semiconductor device comprising:

a first transistor comprising;

a first channel formation region comprising a semiconductor material other than an oxide semiconductor;

a pair of impurity regions provided so as to sandwich the first channel formation region;

a first gate insulating layer over the first channel formation region;

a first gate electrode over the first gate insulating layer; and

a first source electrode electrically connected to one of the pair of impurity regions and a first drain electrode electrically connected to the other one of the pair of impurity regions;

a second transistor comprising;

a second source electrode and a second drain electrode over the first transistor;

a second channel formation region comprising an oxide semiconductor material, and electrically connected to the second source electrode and the second drain electrode;

a second gate insulating layer over the second channel formation region; and

a second gate electrode over the second gate insulating layer; and

a capacitor,

wherein one of the second source electrode and the second drain electrode of the second transistor and one electrode of the capacitor are electrically connected to each other.

2. The semiconductor device according to claim 1, wherein the capacitor comprises.

the second source electrode or the second drain electrode;

the second gate insulating layer; and

an electrode for the capacitor over the second gate insulating layer.

3. The semiconductor device according to claim 1 further comprising:

a third transistor comprising;

a third source electrode and a third drain electrode above the first transistor;

a third channel formation region comprising an oxide semiconductor material, and electrically connected to the third source electrode and the third drain electrode;

a third gate insulating layer over the third channel formation region; and

a third gate electrode over the third gate insulating layer;

a source line;

a bit line;

a word line;

a first signal line; and

a second signal line,

wherein the third gate electrode, one of the second source electrode and the second drain electrode, and the one electrode of the capacitor are electrically connected to one another,

wherein the source line and the third source electrode are electrically connected to each other,

wherein the bit line and the third drain electrode are electrically connected to each other,

wherein the first signal line and the other of the second source electrode and the second drain electrode are electrically connected to each other,

wherein the second signal line and the second gate electrode are electrically connected to each other, and

wherein the word line and the other electrode of the capacitor are electrically connected to each other.

4. The semiconductor device according to claim 1, wherein the semiconductor device comprises a logic circuit or a driver circuit comprising the first transistor.

5. The semiconductor device according to claim 3, wherein the semiconductor device comprises a memory cell comprising the second transistor, the third transistor and the capacitor.

6. The semiconductor device according to claim 1, wherein the semiconductor device comprises a memory cell comprising the second transistor and the capacitor.

7. The semiconductor device according to claim 1, further comprising an interlayer insulating film over the first transistor.

8. The semiconductor device according to claim 7, wherein the interlayer insulating film comprises silicon nitride or silicon oxide.

9. The semiconductor device according to claim 1, wherein the oxide semiconductor material is a material selected from the group consisting of an In—

Sn—

Ga—

Zn—

O-based oxide semiconductor, an In—

Ga—

Zn—

O-based oxide semiconductor, an In—

Sn—

Zn—

O-based oxide semiconductor, an In—

Al—

Zn—

O-based oxide semiconductor, a Sn—

Ga—

Zn—

O-based oxide semiconductor, an Al—

Ga—

Zn—

O-based oxide semiconductor, a Sn—

Al—

Zn—

O-based oxide semiconductor, an In—

Zn—

O-based oxide semiconductor, a Sn—

Zn—

O-based oxide semiconductor, an Al—

Zn—

O-based oxide semiconductor, a Zn—

Mg—

O-based oxide semiconductor, a Sn—

Mg—

O-based oxide semiconductor, an In—

Mg—

O-based oxide semiconductor, an In—

O-based oxide semiconductor, a Sn—

O-based oxide semiconductor, and a Zn—

O-based oxide semiconductor.

10. The semiconductor device according to claim 1, wherein the first channel formation region comprises silicon.

11. The semiconductor device according to claim 1, wherein the semiconductor device is applied to an electronic device selected from the group consisting of a computer, a cellular phone, a portable information terminal, a digital camera, a digital video camera, electronic paper, and a television.