SEMICONDUCTOR DEVICE

• US 20110156028A1
• Filed: 12/27/2010
• Published: 06/30/2011
• Est. Priority Date: 12/28/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Matsuzaki, Takanori, Inoue, Hiroki, Kato, Kiyoshi, Nagatsuka, Shuhei, Koyama, Jun, Yamazaki, Shunpei
• Granted Patent: US 8,450,783 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: G11C 16/0425 comprising cells containing a merged floating gate and select transistor
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H01L 29/788 with floating gate H01L29/78391 takes precedence
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 12/30 DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components
• CPC Class Codes: H10B 43/00 EEPROM devices comprising charge-trapping gate insulators
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

The semiconductor device includes a source line, a bit line, a signal line, a word line, memory cells connected in parallel between the source line and the bit line, a first driver circuit electrically connected to the source line and the bit line through switching elements, a second driver circuit electrically connected to the source line through a switching element, a third driver circuit electrically connected to the signal line, and a fourth driver circuit electrically connected to the word line. The memory cell includes a first transistor including a first gate electrode, a first source electrode, and a first drain electrode, a second transistor including a second gate electrode, a second source electrode, and a second drain electrode, and a capacitor. The second transistor includes an oxide semiconductor material.

Claims

1. A semiconductor device comprising:

a source line;

a bit line;

a signal line;

a word line;

memory cells;

a first driver circuit electrically connected to the source line through a first switching element and electrically connected to the bit line through a second switching element;

a second driver circuit electrically connected to the source line through a third switching element;

a third driver circuit electrically connected to the signal line; and

a fourth driver circuit electrically connected to the word line,

wherein one of the memory cells comprises;

a first transistor comprising a first gate electrode, a first source electrode, and a first drain electrode;

a second transistor comprising a second gate electrode, a second source electrode, and a second drain electrode; and

a capacitor comprising a first terminal and a second terminal,

wherein the second transistor comprises an oxide semiconductor material,

wherein the first gate electrode, one of the second source electrode and the second drain electrode, and the first terminal are electrically connected to one another,

wherein the source line, the first source electrode, and the other of the second source electrode and the second drain electrode are electrically connected to one another,

wherein the bit line and the first drain electrode are electrically connected to each other,

wherein the signal line and the second gate electrode are electrically connected to each other, and

wherein the word line and the second terminal are electrically connected to each other.

2. The semiconductor device according to claim 1, wherein the first transistor comprises a semiconductor material other than an oxide semiconductor.

3. The semiconductor device according to claim 1, wherein the memory cells are connected in parallel between the source line and the bit line.

4. The semiconductor device according to claim 1,

wherein the first transistor comprises:

a channel formation region comprising a semiconductor material other than an oxide semiconductor;

impurity regions provided so that the channel formation region is sandwiched therebetween;

a gate insulating layer over the channel formation region;

the first gate electrode over the gate insulating layer; and

the first source electrode and the first drain electrode electrically connected to the impurity regions.

5. The semiconductor device according to claim 1,

wherein the second transistor comprises:

the second source electrode and the second drain electrode;

a channel formation region comprising the oxide semiconductor material and electrically connected to the second source electrode and the second drain electrode;

a gate insulating layer over the channel formation region; and

the second gate electrode over the gate insulating layer.

6. The semiconductor device according to claim 5,

wherein the capacitor comprises:

the second source electrode or the second drain electrode;

an oxide semiconductor layer comprising the oxide semiconductor material;

the gate insulating layer; and

an electrode for the capacitor over the gate insulating layer.

7. The semiconductor device according to claim 2, wherein single crystal silicon is used as the semiconductor material.

8. The semiconductor device according to claim 1, wherein the first transistor operates at higher speed than the second transistor.

9. A semiconductor device comprising:

a source line;

a bit line;

a signal line;

a word line;

memory cells;

a first driver circuit electrically connected to the source line through a first switching element and electrically connected to the bit line through a second switching element;

a second driver circuit electrically connected to the bit line through a third switching element;

a third driver circuit electrically connected to the signal line; and

a fourth driver circuit electrically connected to the word line,

wherein one of the memory cells comprises;

a first transistor comprising a first gate electrode, a first source electrode, and a first drain electrode;

a second transistor comprising a second gate electrode, a second source electrode, and a second drain electrode; and

a capacitor comprising a first terminal and a second terminal,

wherein the second transistor comprises an oxide semiconductor material,

wherein the first gate electrode, one of the second source electrode and the second drain electrode, and the first terminal are electrically connected to one another,

wherein the source line and the first source electrode are electrically connected to each other,

wherein the bit line, the first drain electrode and the other of the second source electrode and the second drain electrode are electrically connected to one another,

wherein the signal line and the second gate electrode are electrically connected to each other, and

wherein the word line and the second terminal are electrically connected to each other.

10. The semiconductor device according to claim 9, wherein the first transistor comprises a semiconductor material other than an oxide semiconductor.

11. The semiconductor device according to claim 9, wherein the memory cells are connected in parallel between the source line and the bit line.

12. The semiconductor device according to claim 9,

wherein the first transistor comprises:

a channel formation region comprising a semiconductor material other than an oxide semiconductor;

impurity regions provided so that the channel formation region is sandwiched therebetween;

a gate insulating layer over the channel formation region;

the first gate electrode over the gate insulating layer; and

the first source electrode and the first drain electrode electrically connected to the impurity regions.

13. The semiconductor device according to claim 9,

wherein the second transistor comprises:

the second source electrode and the second drain electrode;

a channel formation region comprising the oxide semiconductor material and electrically connected to the second source electrode and the second drain electrode;

a gate insulating layer over the channel formation region; and

the second gate electrode over the gate insulating layer.

14. The semiconductor device according to claim 13,

wherein the capacitor comprises:

the second source electrode or the second drain electrode;

an oxide semiconductor layer comprising the oxide semiconductor material;

the gate insulating layer; and

an electrode for the capacitor over the gate insulating layer.

15. The semiconductor device according to claim 10, wherein single crystal silicon is used as the semiconductor material.

16. The semiconductor device according to claim 9, wherein the first transistor operates at higher speed than the second transistor.

17. A semiconductor device comprising:

n (n is a natural number) bit lines;

l (l is the smallest natural number greater than or equal to n/2) source lines;

m (m is a natural number) signal lines;

m word lines;

m×

n memory cells;

a first driver circuit electrically connected to one of the l source lines through a first switching element and electrically connected to one of the n bit lines through a second switching element;

a second driver circuit electrically connected to the one of the n bit lines through a third switching element;

a third driver circuit electrically connected to one of the m signal lines; and

a fourth driver circuit electrically connected to one of the m word lines,

wherein one of the m×

n memory cells comprises;

a first transistor comprising a first gate electrode, a first source electrode, and a first drain electrode;

a second transistor comprising a second gate electrode, a second source electrode, and a second drain electrode; and

a capacitor comprising a first terminal and a second terminal,

wherein the second transistor comprises an oxide semiconductor material,

wherein the first gate electrode, one of the second source electrode and the second drain electrode, and the first terminal are electrically connected to one another,

wherein one of the l source lines and the first source electrode are electrically connected to each other,

wherein one of the n bit lines, the first drain electrode, and the other of the second source electrode and the second drain electrode are electrically connected to one another,

wherein one of the m signal lines and the second gate electrode are electrically connected to each other,

wherein one of the m word lines and the second terminal are electrically connected to each other,

wherein the one of the l source lines is electrically connected to a first source electrode of another of the m×

n memory cells, and the another of the m×

n memory cells is adjacent to the one of the m×

n memory cells, and

wherein a first drain electrode of the another of the m×

n memory cells is electrically connected to another of the n bit lines.

18. The semiconductor device according to claim 17, wherein the first transistor comprises a semiconductor material other than an oxide semiconductor.

19. The semiconductor device according to claim 17,

wherein the second switching element is configured to be turned on during the third switching element is turned off, and the third switching element is configured to be turned on during the third switching element is turned off.

20. The semiconductor device according to claim 17,

wherein the first transistor comprises:

a channel formation region comprising a semiconductor material other than an oxide semiconductor;

impurity regions provided so that the channel formation region is sandwiched therebetween;

a gate insulating layer over the channel formation region;

the first gate electrode over the gate insulating layer; and

the first source electrode and the first drain electrode electrically connected to the impurity regions.

21. The semiconductor device according to claim 17,

wherein the second transistor comprises:

the second source electrode and the second drain electrode;

a channel formation region comprising the oxide semiconductor material and electrically connected to the second source electrode and the second drain electrode;

a gate insulating layer over the channel formation region; and

the second gate electrode over the gate insulating layer.

22. The semiconductor device according to claim 21,

wherein the capacitor comprises:

the second source electrode or the second drain electrode;

an oxide semiconductor layer comprising the oxide semiconductor material;

the gate insulating layer; and

an electrode for the capacitor over the gate insulating layer.

23. The semiconductor device according to claim 18, wherein single crystal silicon is used as the semiconductor material.

24. The semiconductor device according to claim 17, wherein the first transistor operates at higher speed than the second transistor.