Self-aligned contacts

• US 20110156107A1
• Filed: 12/30/2009
• Published: 06/30/2011
• Est. Priority Date: 12/30/2009
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Mackiewicz, Ryan, Klaus, Jason W., Rahhal-Orabi, Nadia M., Joshi, Subhash M., Hwang, Jack, Ghani, Tahir, Bohr, Mark T., Steigerwald, Joseph M.
• Granted Patent: US 8,436,404 B2
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: H01L 2029/7858 having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts
• CPC Class Codes: H01L 21/28123 Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
• CPC Class Codes: H01L 21/28229 by deposition of a layer, e.g. metal, metal compound or poysilicon, followed by transformation thereof into an insulating layer
• CPC Class Codes: H01L 21/28255 the insulator being formed after the semiconductor body, the semiconductor belonging to Group IV and not being elemental silicon, e.g. Ge, SiGe, SiGeC
• CPC Class Codes: H01L 21/283 Deposition of conductive or insulating materials for electrodes conducting electric current
• CPC Class Codes: H01L 21/28562 Selective deposition
• CPC Class Codes: H01L 21/31105 Etching inorganic layers
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/535 including internal interconnections, e.g. cross-under constructions internal lead connections H01L23/481
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/456 : on silicon
• CPC Class Codes: H01L 29/495 : the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4966 : the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/512 : the variation being parallel to the channel plane
• CPC Class Codes: H01L 29/517 : the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 : the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66477 : with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/665 : using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6653 : using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 : using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 : using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/78 : with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/785 : having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

Claims

1. A transistor comprising:

a substrate;

a pair of spacers on the substrate;

a gate dielectric layer on the substrate and between the pair of spacers;

a gate electrode layer on the gate dielectric layer and between the pair of spacers;

an insulating cap layer on the gate electrode layer and between the pair of spacers; and

a pair of diffusion regions adjacent to the pair of spacers.

2. The transistor of claim 1, wherein a height of the combination of the gate dielectric layer, the gate electrode layer, and the insulating cap layer does not exceed a height of the pair of spacers.

3. The transistor of claim 1, wherein the gate dielectric layer is formed along the surface of the substrate and along sidewalls of the pair of spacers.

4. The transistor of claim 1, wherein the insulating cap layer comprises silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, silicon oxynitride, or aluminum oxide.

5. The transistor of claim 1, wherein the insulating cap layer comprises a nitride material, a carbide material, an oxide material, a metal oxide material, or a low-k dielectric material.

6. The transistor of claim 1, wherein the insulating cap layer comprises boron nitride or boron carbide.

7. The transistor of claim 1, wherein the insulating cap layer comprises a low-k dielectric material doped with one or more of carbon, nitrogen, and hydrogen.

8. A method of forming a transistor comprising:

forming a gate dielectric layer on a substrate;

forming a gate electrode layer on the gate dielectric layer;

forming a pair of spacers on opposing sides of the gate dielectric layer and the gate electrode layer;

forming a pair of diffusion regions adjacent to the pair of spacers;

recessing the gate electrode layer; and

forming an insulating cap layer on the recessed gate electrode layer within the pair of spacers.

9. The method of claim 8, wherein the forming of the insulating cap layer comprises:

depositing a blanket layer of an insulating material over the recessed gate electrode layer; and

planarizing the insulating material layer to form the insulating cap layer.

10. The method of claim 8, further comprising:

removing the gate electrode layer and the gate dielectric layer after the diffusion regions have been formed, thereby forming a trench between the pair of spacers;

depositing a conformal low-k gate dielectric layer along the sidewalls and bottom surface of the trench between the spacers; and

depositing a metal gate electrode layer on the low-k gate dielectric layer before recessing the metal gate electrode.

11. The method of claim 8, wherein the insulating cap layer comprises silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, silicon oxynitride, or aluminum oxide.

12. The method of claim 8, wherein the insulating cap layer comprises a nitride material, a carbide material, an oxide material, a metal oxide material, or a low-k dielectric material.

13. The method of claim 8, wherein the insulating cap layer comprises boron nitride or boron carbide.

14. The method of claim 8, wherein the insulating cap layer comprises a low-k dielectric material doped with one or more of carbon, nitrogen, and hydrogen.

15. A method of forming a transistor comprising:

forming a gate stack on a substrate, the gate stack comprising a gate dielectric layer, a gate electrode layer on the gate dielectric layer, and an insulating cap layer on the gate electrode layer;

forming a pair of spacers on opposing sides of the gate stack; and

forming a pair of diffusion regions adjacent to the pair of spacers;

16. The method of claim 15, wherein the insulating cap layer comprises silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, silicon oxynitride, or aluminum oxide.

17. The method of claim 15, wherein the insulating cap layer comprises a nitride material, a carbide material, an oxide material, a metal oxide material, or a low-k dielectric material.

18. The method of claim 15, wherein the insulating cap layer comprises boron nitride or boron carbide.

19. The method of claim 15, wherein the insulating cap layer comprises a low-k dielectric material doped with one or more of carbon, nitrogen, and hydrogen.

20. A transistor comprising:

a substrate;

a pair of spacers on the substrate;

a gate dielectric layer on the substrate and between the pair of spacers;

a gate electrode layer on the gate dielectric layer and between the pair of spacers;

an insulating cap layer sited atop the gate electrode layer that extends laterally over the top surfaces of the pair of spacers; and

a pair of diffusion regions adjacent to the pair of spacers.

21. The transistor of claim 20, wherein the gate dielectric layer is formed along the surface of the substrate and along sidewalls of the pair of spacers.

22. The transistor of claim 20, wherein the insulating cap layer comprises silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, silicon oxynitride, or aluminum oxide.

23. The transistor of claim 20, wherein the insulating cap layer comprises a nitride material, a carbide material, an oxide material, a metal oxide material, or a low-k dielectric material.

24. The transistor of claim 20, wherein the insulating cap layer comprises boron nitride or boron carbide.

25. The transistor of claim 20, wherein the insulating cap layer comprises a low-k dielectric material doped with one or more of carbon, nitrogen, and hydrogen.

26. The transistor of claim 20, wherein the pair of spacers comprises silicon oxynitride, carbon-doped silicon oxynitride, or a low-k dielectric material.

27. A method of forming a transistor comprising:

forming a gate dielectric layer on a substrate;

forming a gate electrode layer on the gate dielectric layer;

forming a pair of spacers on opposing sides of the gate dielectric layer and the gate electrode layer;

forming a pair of diffusion regions adjacent to the pair of spacers;

recessing the gate electrode layer;

recessing the pair of spacers; and

forming an insulating cap layer on the recessed gate electrode layer that extends laterally over the top surfaces of the recessed pair of spacers.

28. The method of claim 27, further comprising:

removing the recessed gate electrode layer and the gate dielectric layer after the spacers have been recessed, thereby forming a trench between the recessed pair of spacers;

depositing a conformal low-k gate dielectric layer along the sidewalls and bottom surface of the trench between the recessed pair of spacers;

depositing a metal gate electrode layer on the low-k gate dielectric layer; and

recessing the metal gate electrode so that a height of the recessed metal gate electrode is similar to a height of the recessed pair of spacers before the insulating cap layer is formed.

29. The method of claim 27, wherein the forming of the insulating cap layer comprises:

depositing a blanket layer of an insulating material over the recessed gate electrode layer and recessed pair of spacers; and

planarizing the insulating material layer to form the insulating cap layer.

30. The method of claim 27, wherein a height of the recessed pair of spacers is substantially the same as a height of the recessed gate electrode.

31. The method of claim 27, wherein the pair of spacers comprises silicon oxynitride (SiON), carbon-doped silicon oxynitride (SiOCN), or a low-k dielectric material.

32. A transistor comprising:

a substrate;

a pair of spacers on the substrate;

a gate dielectric layer on the substrate and between the pair of spacers;

a gate electrode layer having a stepped profile on the gate dielectric layer, wherein a middle portion of the gate electrode layer has a relatively larger height than side portions of the gate electrode layer;

an insulating cap layer on the gate electrode layer and between the pair of spacers; and

a pair of diffusion regions adjacent to the pair of spacers.

33. The transistor of claim 32, wherein the insulating cap layer comprises silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, silicon oxynitride, or aluminum oxide.

34. The transistor of claim 32, wherein the insulating cap layer comprises a nitride material, a carbide material, an oxide material, a metal oxide material, or a low-k dielectric material.

35. The transistor of claim 32, wherein the insulating cap layer comprises boron nitride or boron carbide.

36. The transistor of claim 32, wherein the insulating cap layer comprises a low-k dielectric material doped with one or more of carbon, nitrogen, and hydrogen.

37. The transistor of claim 32, wherein the gate electrode comprises two metal layers, wherein a first metal layer comprises the middle portion of the gate electrode having the relatively larger height and a second metal layer comprises the side portions of the gate electrode.

38. A method of forming a transistor comprising:

forming a gate dielectric layer on a substrate;

forming a gate electrode layer on the gate dielectric layer;

forming a pair of spacers on opposing sides of the gate dielectric layer and the gate electrode layer;

forming a pair of diffusion regions adjacent to the pair of spacers;

removing the gate electrode layer and the gate dielectric layer, thereby forming a trench between the pair of spacers;

depositing a conformal first metal layer within the trench;

depositing a second metal layer on the first metal layer;

recessing the first and second metal layers, wherein the first metal layer is recessed to a larger extent than the second metal layer; and

forming an insulating cap layer on the recessed first and second metal layers.

39. The method of claim 38, wherein the recessing of the first and second metal layers comprises:

applying an etch chemistry to the first and second metal layers that is selective to the second metal layer.

40. The method of claim 38, wherein the recessing of the first and second metal layers comprises:

applying a first etch chemistry to recess the first metal layer; and

applying a second etch chemistry to recess the second metal layer,

wherein the first and second etch chemistries recess the first metal layer to a larger extent than the second metal layer.

41. The method of claim 40, wherein the second etch chemistry also recesses the first metal layer.

42. The method of claim 38, wherein the forming of the insulating cap layer comprises:

depositing a blanket layer of an insulating material over the recessed first and second metal layers; and

planarizing the insulating material layer to form the insulating cap layer.

43. The method of claim 38, wherein the insulating cap layer comprises silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, silicon oxynitride, or aluminum oxide.

44. The method of claim 38, wherein the insulating cap layer comprises a nitride material, a carbide material, an oxide material, a metal oxide material, or a low-k dielectric material.

45. The method of claim 38, wherein the insulating cap layer comprises boron nitride or boron carbide.

46. The method of claim 38, wherein the insulating cap layer comprises a low-k dielectric material doped with one or more of carbon, nitrogen, and hydrogen.

47. A transistor comprising:

a substrate;

a pair of spacers on the substrate;

a gate dielectric layer on the substrate and between the pair of spacers;

a gate electrode layer having a stepped profile on the gate dielectric layer, wherein a middle portion of the gate electrode layer has a relatively larger height than side portions of the gate electrode layer;

an insulating cap layer sited atop the gate electrode layer that extends laterally over the top surfaces of the pair of spacers; and

a pair of diffusion regions adjacent to the pair of spacers.

48. The transistor of claim 47, wherein the insulating cap layer comprises silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, silicon oxynitride, or aluminum oxide.

49. The transistor of claim 47, wherein the insulating cap layer comprises a nitride material, a carbide material, an oxide material, a metal oxide material, or a low-k dielectric material.

50. The transistor of claim 47, wherein the insulating cap layer comprises boron nitride or boron carbide.

51. The transistor of claim 47, wherein the insulating cap layer comprises a low-k dielectric material doped with one or more of carbon, nitrogen, and hydrogen.

52. The transistor of claim 47, wherein the gate electrode comprises two metal layers, wherein a first metal layer comprises the middle portion of the gate electrode having the relatively larger height and a second metal layer comprises the side portions of the gate electrode.