SEMICONDUCTOR DEVICE

• US 20110156117A1
• Filed: 12/22/2010
• Published: 06/30/2011
• Est. Priority Date: 12/25/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kato, Kiyoshi, Koyama, Jun, Yamazaki, Shunpei
• Granted Patent: US 8,482,001 B2
• Time in Patent Office: Days
• US Class Current: 257/300
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/11803 using field effect technology
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/125 the MOSFET being a thin film transistor [TFT]
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/30 DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

An object of the present invention is to provide a semiconductor device having a novel structure in which in a data storing time, stored data can be stored even when power is not supplied, and there is no limitation on the number of writing. A semiconductor device includes a first transistor including a first source electrode and a first drain electrode; a first channel formation region for which an oxide semiconductor material is used and to which the first source electrode and the first drain electrode are electrically connected; a first gate insulating layer over the first channel formation region; and a first gate electrode over the first gate insulating layer. One of the first source electrode and the first drain electrode of the first transistor and one electrode of a capacitor are electrically connected to each other.

Claims

1. A semiconductor device comprising:

a transistor comprising;

a source electrode and a drain electrode;

an oxide semiconductor layer overlapping with the source electrode and the drain electrode; and

a gate insulating layer overlapping with the oxide semiconductor layer, and

a capacitor,

wherein one of the source electrode and the drain electrode of the transistor and one electrode of the capacitor are electrically connected to each other.

2. The semiconductor device according to claim 1,

wherein the capacitor comprises the source electrode or the drain electrode, the gate insulating layer, and an electrode for the capacitor over the gate insulating layer.

3. The semiconductor device according to claim 1,

wherein edge portions of the source electrode and the drain electrode are tapered.

4. The semiconductor device according to claim 1,

wherein side surfaces of the source electrode and the drain electrode are oxidized.

5. The semiconductor device according to claim 1,

wherein the oxide semiconductor layer comprises crystals whose c-axis is oriented in a direction perpendicular to a surface of the oxide semiconductor layer.

6. The semiconductor device according to claim 1,

wherein the oxide semiconductor layer has a two-layer structure.

7. The semiconductor device according to claim 1,

wherein the transistor is formed over a glass substrate, a ceramic substrate, a quartz substrate, or a sapphire substrate.

8. The semiconductor device according to claim 1,

wherein the transistor is formed over a flexible substrate.

9. The semiconductor device according to claim 1,

wherein a hydrogen concentration of the oxide semiconductor layer is 5×

10¹⁹ atoms/cm³ or lower.

10. The semiconductor device according to claim 1,

wherein the semiconductor device comprises a non-volatile memory device.

11. A semiconductor device comprising:

a first transistor comprising;

a first source electrode and a first drain electrode;

a first oxide semiconductor layer overlapping with the first source electrode and the first drain electrode;

a first gate insulating layer overlapping with the first oxide semiconductor layer; and

a first gate electrode overlapping with the first gate insulating layer, a second transistor comprising;

a second source electrode and a second drain electrode;

a second oxide semiconductor layer overlapping with the second source electrode and the second drain electrode;

a second gate insulating layer overlapping with the second oxide semiconductor layer; and

a second gate electrode overlapping with the second gate insulating layer,

a capacitor;

a source line;

a bit line;

a word line;

a first signal line; and

a second signal line,

wherein the second gate electrode, one of the first source electrode and the first drain electrode, and one electrode of the capacitor are electrically connected to one another,

wherein the source line and the second source electrode are electrically connected to each other,

wherein the bit line and the second drain electrode are electrically connected to each other,

wherein the first signal line and the other of the first source electrode and the first drain electrode are electrically connected to each other,

wherein the second signal line and the first gate electrode are electrically connected to each other, and

wherein the word line and the other electrode of the capacitor are electrically connected to each other.

12. The semiconductor device according to claim 11,

wherein the capacitor comprises the first source electrode or the first drain electrode, the first gate insulating layer, and an electrode for the capacitor over the first gate insulating layer.

13. The semiconductor device according to claim 11,

wherein edge portions of the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode are tapered.

14. The semiconductor device according to claim 11,

wherein side surfaces of the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode are oxidized.

15. The semiconductor device according to claim 11,

wherein at least one of the first oxide semiconductor layer and the second oxide semiconductor layer comprises crystals whose c-axis is oriented in a direction perpendicular to a surface of the first oxide semiconductor layer or the second oxide semiconductor layer.

16. The semiconductor device according to claim 11,

wherein at least one of the first oxide semiconductor layer and the second oxide semiconductor layer has a two-layer structure.

17. The semiconductor device according to claim 11,

wherein the first transistor and the second transistor are formed over a glass substrate, a ceramic substrate, a quartz substrate, or a sapphire substrate.

18. The semiconductor device according to claim 11,

wherein the first transistor and the second transistor are formed over a flexible substrate.

19. The semiconductor device according to claim 11,

wherein a hydrogen concentration of at least one of the first oxide semiconductor layer and the second oxide semiconductor layer is 5×

10¹⁹ atoms/cm³ or lower.

20. The semiconductor device according to claim 11,

wherein the semiconductor device comprises a non-volatile memory device.