Interwafer interconnects for stacked CMOS image sensors

• US 20110156197A1
• Filed: 12/31/2009
• Published: 06/30/2011
• Est. Priority Date: 12/31/2009
• Status: Abandoned Application

• Current Assignee: Omnivision Technologies Incorporated (Will Semiconductor Co., Ltd. Shanghai)
• Original Assignee: Omnivision Technologies Incorporated (Will Semiconductor Co., Ltd. Shanghai)
• Inventors: Tivarus, Cristian A., McCarten, John P., Summa, Joseph R.
• Application Number:
  US12/655,549
• Publication Number:
  US 20110156197A1
• Time in Patent Office: Days
• US Class Current: 257/444
• CPC Class Codes: H01L 27/14634 Assemblies, i.e. Hybrid structures
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/1469 Assemblies, i.e. hybrid integration

Abstract

An image sensor includes a sensor wafer and a circuit wafer electrically connected to the sensor wafer. The sensor wafer includes unit cells with each unit cell having at least one photodetector and a charge-to-voltage conversion region. The circuit wafer includes unit cells with each unit cell having an electrical node associated with each unit cell on the sensor wafer. An inter-wafer interconnect is connected between each unit cell on the sensor wafer and a respective unit cell on the circuit wafer. The location of at least a portion of the inter-wafer interconnects is shifted or disposed at a different location with respect to the location of one or both components connected to the shifted inter-wafer interconnects. The locations of the inter-wafer interconnects can be disposed at different locations with respect to the locations of the charge-to-voltage conversion regions or with respect to the locations of the electrical nodes.

Claims

1. An image sensor, comprising:

a sensor wafer comprising a first plurality of unit cells with each unit cell including at least one photodetector and a charge-to-voltage conversion region;

a circuit wafer comprising a second plurality of unit cells each including an electrical node associated with each unit cell on the sensor wafer;

an inter-wafer interconnect electrically connected between each charge-to-voltage conversion region on the sensor wafer and a respective electrical node on the circuit wafer, wherein a location of at least a portion of the inter-wafer interconnects is shifted a predetermined distance with respect to a location of the charge-to-voltage conversion region or the electrical node connected to each shifted inter-wafer interconnects; and

a conductive layer electrically connected between each shifted inter-wafer interconnect and the charge-to-voltage conversion region or the electrical node connected to the shifted inter-wafer interconnect.

2. The image sensor of claim 1, wherein the location of at least a portion of the inter-wafer interconnects are shifted a predetermined distance with respect to the location of each charge-to-voltage conversion region on the sensor wafer connected to shifted inter-wafer interconnects.

3. The image sensor of claim 1, wherein the location of at least a portion of the inter-wafer interconnects are shifted a predetermined distance with respect to the location of each electrical node on the circuit wafer connected to shifted inter-wafer interconnects.

4. The image sensor of claim 1, wherein the location of at least a portion of the inter-wafer interconnects are shifted a predetermined distance with respect to the location of each charge-to-voltage conversion region on the sensor wafer and with respect to each electrical node on the circuit wafer connected to shifted inter-wafer interconnects.

5. The image sensor of claim 1, wherein each electrical node on the circuit wafer connects to a charge-to-voltage conversion region on the circuit wafer.

6. The image sensor of claim 1, wherein each electrical node on the circuit wafer connects to a gate of an amplifier on the circuit wafer.

7. The image sensor of claim 1, wherein each unit cell on the sensor wafer includes two photodetectors and a shared charge-to-voltage conversion region.

8. The image sensor of claim 1, wherein each unit cell on the sensor wafer includes four photodetectors and a shared charge-to-voltage conversion region.

9. An image capture device, comprising:

an image sensor, comprising;

a sensor wafer comprising a first plurality of unit cells with each unit cell including at least one photodetector and a charge-to-voltage conversion region;

a circuit wafer comprising a second plurality of unit cells each including an electrical node associated with each unit cell on the sensor wafer;

an inter-wafer interconnect connected between each charge-to-voltage conversion region on the sensor wafer and a respective electrical node on the circuit wafer, wherein a location of at least a portion of the inter-wafer interconnects is shifted a predetermined distance with respect to a location of the charge-to-voltage conversion region or the electrical node connected to each shifted inter-wafer interconnects; and

a conductive layer electrically connected between each shifted inter-wafer interconnect and the charge-to-voltage conversion region or the electrical node connected to the shifted inter-wafer interconnect.

10. The image capture device of claim 9, wherein the location of at least a portion of the inter-wafer interconnects are shifted a predetermined distance with respect to the location of each charge-to-voltage conversion region on the sensor wafer connected to shifted inter-wafer interconnects.

11. The image capture device of claim 9, wherein the location of at least a portion of the inter-wafer interconnects are shifted a predetermined distance with respect to the location of each electrical node on the circuit wafer connected to shifted inter-wafer interconnects.

12. The image capture device of claim 9, wherein the location of at least a portion of the inter-wafer interconnects are shifted a predetermined distance with respect to the location of each charge-to-voltage conversion region on the sensor wafer and with respect to each electrical node on the circuit wafer connected to shifted inter-wafer interconnects.

13. The image capture device of claim 9, wherein each electrical node on the circuit wafer connects to a charge-to-voltage conversion region on the circuit wafer.

14. The image capture device of claim 9, wherein each electrical node on the circuit wafer connects to a gate of an amplifier on the circuit wafer.

15. The image capture device of claim 9, wherein each unit cell on the sensor wafer includes two photodetectors and a shared charge-to-voltage conversion region.

16. The image capture device of claim 9, wherein each unit cell on the sensor wafer includes four photodetectors and a shared charge-to-voltage conversion region.