SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

• US 20110156242A1
• Filed: 12/16/2010
• Published: 06/30/2011
• Est. Priority Date: 12/24/2009
• Status: Active Grant

• Current Assignee: Shinko Electric Industries Company Limited (Fujitsu Limited)
• Original Assignee: Shinko Electric Industries Company Limited (Fujitsu Limited)
• Inventors: Shiraishi, Akinori, Murayama, Kei, Higashi, Mitsutoshi, Taguchi, Yuichi, Sakaguchi, Hideaki
• Granted Patent: US 8,227,909 B2
• Time in Patent Office: Days
• US Class Current: 257/698
• CPC Class Codes: B81B 2207/096 through the substrate
• CPC Class Codes: B81C 1/00269 Bonding of solid lids or wafers to the substrate
• CPC Class Codes: B81C 1/00301 Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
• CPC Class Codes: B81C 1/00888 Multistep processes involving only mechanical separation, e.g. grooving followed by cleaving
• CPC Class Codes: B81C 2203/0118 Bonding a wafer on the substrate, i.e. where the cap consists of another wafer
• CPC Class Codes: H01L 21/50 Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
• CPC Class Codes: H01L 2224/83805 involving forming a eutectic alloy at the bonding interface
• CPC Class Codes: H01L 23/10 characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 24/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01049 Indium [In]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

There is provided a method of manufacturing a semiconductor package. The method includes: (a) providing a silicon wafer comprising a first surface and a second surface opposite to the first surface; (b) forming vias through the silicon wafer in its thickness direction; (c) forming wiring patterns on the first surface of the silicon wafer such that the wiring patterns are electrically connected to the vias; (d) bonding a MEMS element wafer comprising MEMS elements onto the second surface of the silicon wafer such that the MEMS elements are electrically connected to the vias; (e) dividing the MEMS element wafer into the respective MEMS elements; (f) bonding a lid having concave portions therein onto the second surface of the silicon wafer such that the respective MEMS elements face a corresponding one of the concave portions; and (g) dicing the lid and the silicon wafer.

Claims

1. A method of manufacturing a semiconductor package, comprising:

(a) providing a silicon wafer comprising a first surface and a second surface opposite to the first surface;

(b) forming vias through the silicon wafer in its thickness direction;

(c) forming wiring patterns on the first surface of the silicon wafer such that the wiring patterns are electrically connected to the vias;

(d) bonding a MEMS element wafer comprising MEMS elements onto the second surface of the silicon wafer such that the MEMS elements are electrically connected to the vias;

(e) dividing the MEMS element wafer into the respective MEMS elements;

(f) bonding a lid having concave portions therein onto the second surface of the silicon wafer such that the respective MEMS elements face a corresponding one of the concave portions; and

(g) dicing the lid and the silicon wafer.

2. A method of manufacturing a semiconductor package, comprising:

(a) providing a silicon wafer comprising a first surface and a second surface opposite to the first surface;

(b) forming vias through the silicon wafer in its thickness direction;

(c) forming wiring patterns on the first surface of the silicon wafer such that the wiring patterns are electrically connected to the vias;

(d) bonding a MEMS element wafer comprising MEMS elements onto the second surface of the silicon wafer such that the MEMS elements are electrically connected to the vias;

(e) bonding a lid having concave portions therein onto the MEMS element wafer such that the respective MEMS elements face a corresponding one of the concave portions; and

(f) dicing the lid, the MEMS element wafer and the silicon wafer.

3. The method according to claim 2, further comprising:

(h) forming grooves between the respective concave portions such that the respective grooves extend from the first surface of the silicon wafer to a portion of the lid in the thickness direction; and

(i) coating an inner wall surface and an inner bottom surface of the respective grooves with a metal through plating, and

wherein step (f) comprises;

dicing the lid, the MEMS element wafer and the silicon wafer along the grooves.

4. The method according to claim 2, wherein step (e) comprises:

bonding the lid onto the MEMS element wafer under a vacuum environment.

5. A method of manufacturing a semiconductor package, comprising:

(a) providing a silicon wafer comprising a first surface and a second surface opposite to the first surface;

(b) forming vias through the silicon wafer in its thickness direction;

(c) forming wiring patterns on the first surface of the silicon wafer such that the wiring patterns are electrically connected to the vias;

(d) bonding a MEMS element wafer comprising MEMS elements onto the second surface of the silicon wafer such that the MEMS elements are electrically connected to the vias;

(e) providing a lid having concave portions therein and vent holes therethrough, each of the vent holes being in communication with a corresponding one of the concave portions;

(f) bonding the lid onto the MEMS element wafer such that the respective MEMS elements face a corresponding one of the concave portions;

(g) sealing the vent holes under a vacuum environment; and

(h) dicing the lid, the MEMS element wafer and the silicon wafer.

6. The method according to claim 5, further comprising:

(i) forming grooves between the respective concave portions such that the respective grooves extend from the first surface of the silicon wafer to a portion of the lid in the thickness direction; and

(j) coating an inner wall surface and an inner bottom surface of the respective grooves with a metal through plating, and

wherein step (h) comprises;

dicing the lid, the MEMS element wafer and the silicon wafer along the grooves.

7. A method of manufacturing a semiconductor package, comprising:

(a) providing a silicon wafer comprising a first surface and a second surface opposite to the first surface;

(b) forming vias through the silicon wafer in its thickness direction;

(c) forming wiring patterns on the first surface of the silicon wafer such that the wiring patterns are electrically connected to the vias;

(d) forming posts on the second surface of the silicon wafer;

(e) bonding a MEMS element wafer comprising MEMS elements onto the second surface of the silicon wafer such that the MEMS elements are electrically connected to the vias and such that the posts project from the MEMS element wafer;

(f) bonding protection covers onto the posts such that the respective protection covers cover a corresponding one of the respective MEMS elements;

(g) forming a metal layer on the second surface of the silicon wafer and on the respective protection covers;

(h) bonding a lid having concave portions therein onto the metal layer through a metal boding material, such that the respective MEMS elements face a corresponding one of the concave portions; and

(i) dicing the lid, the MEMS element wafer and the silicon wafer.

8. A semiconductor package, comprising:

a first substrate comprising a first surface and a second surface opposite to the First surface;

a wiring pattern on the first surface of the first substrate;

a MEMS element comprising an electrical connection region and a bonding region surrounding the electrical connection region, wherein the MEMS element is electrically connected to the wiring pattern in the electrical connection region, and the MEMS element is bonded on the second surface of the first substrate through a first bonding material in the bonding region;

a second substrate having a concave portion therein and being bonded on the MEMS element through a second bonding material so as to hermetically seal the MEMS element, wherein the second bonding material is provided in the bonding region of the MEMS element; and

a metal film formed on the first and second bonding materials, a side surface of the MEMS element, a side surface of the first substrate and a side surface of the second substrate.