INTEGRATED TRENCH GUARDED SCHOTTKY DIODE COMPATIBLE WITH POWERDIE, STRUCTURE AND METHOD

• US 20110156679A1
• Filed: 11/03/2010
• Published: 06/30/2011
• Est. Priority Date: 12/30/2009
• Status: Active Grant

• Current Assignee: Intersil Americas LLC (Renesas Electronics Corporation)
• Original Assignee: Intersil Americas LLC (Renesas Electronics Corporation)
• Inventors: Hebert, Francois, Girdhar, Dev Alok
• Granted Patent: US 8,492,225 B2
• Time in Patent Office: Days
• US Class Current: 323/282
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method and structure for a voltage converter including a trench field effect transistor (FET) and a trench guarded Schottky diode which is integrated with the trench FET. In an embodiment, a voltage converter can include a lateral FET, a trench FET, and a trench guarded Schottky diode integrated with the trench FET. A method to form a voltage converter can include the formation of a trench FET gate, a trench guarded Schottky diode gate, and a lateral FET gate using a single conductive layer such as a polysilicon layer.

Claims

1. A semiconductor device circuit stage, comprising:

a semiconductor die, comprising;

a circuit side;

a non-circuit side opposite the circuit side;

a circuit stage, comprising;

a high-side transistor comprising a lateral field effect transistor (FET) and a source region for the lateral field effect transistor;

a low-side transistor comprising a trench FET, a drain region for the trench FET which is electrically coupled with the source region of the lateral FET, and a source region for the trench FET;

a trench guarded Schottky diode integrated into the semiconductor die, wherein an anode of the trench guarded Schottky diode is electrically coupled with the source region of the trench FET and a cathode of the trench guarded Schottky diode is electrically coupled with the drain region of the trench FET and the source region of the lateral FET; and

an output provided on the non-circuit side of the semiconductor die,

wherein the trench guarded Schottky diode is integrated into a cell of the trench FET.

2. The semiconductor device circuit stage of claim 1, further comprising:

an upper surface of a trench gate of the trench FET is above an upper surface of a trench gate of the trench guarded Schottky diode.

3. The semiconductor device circuit stage of claim 1, further comprising:

the source of the trench FET which is electrically coupled to a gate of the trench guarded Schottky diode through a metal layer.

4. The semiconductor device circuit stage of claim 3, further comprising:

an upper surface of the gate of the trench guarded Schottky diode; and

a doped body region having an upper surface,

wherein the upper surface of the gate of the trench guarded Schottky diode is below the upper surface of the body region.

5. The semiconductor device circuit stage of claim 1, further comprising:

a trench conductor which electrically couples the source of the lateral FET to a semiconductor substrate.

6. The semiconductor device of claim 1, further comprising:

a metal layer on the non-circuit side of the semiconductor die, wherein an output of the semiconductor device circuit stage is electrically coupled to the metal layer.

7. The semiconductor device of claim 1 wherein a forward voltage drop of the trench guarded Schottky diode is about 300 mV lower that of the trench FET at any given current.

8. A method of integrating a Schottky diode in a trench field effect transistor (FET), comprising:

etching at least one opening through a field oxidation layer and into a semiconductor substrate to form at least one Schottky diode trench gate opening;

etching at least one opening into the semiconductor substrate to form at least one trench FET gate opening;

growing a gate oxide layer in the at least one Schottky diode trench gate opening and the at least one trench FET gate opening;

depositing polysilicon within the at least one Schottky diode trench gate opening and the at least one trench FET gate opening to fill at least a portion of the at least one Schottky diode trench gate opening and at least a portion of the at least one trench FET gate opening; and

etching the field oxide layer and at least a portion of the polysilicon within the Schottky diode trench gate opening.

9. The method of claim 8, further comprising:

forming at least one Schottky diode trench gate having, in cross section, a first portion and a second portion, wherein the field oxide layer is interposed between the first portion and the second portion of the Schottky diode trench gate; and

implanting a dopant into the semiconductor substrate, wherein the field oxide layer masks dopant implantation into the semiconductor substrate between the first portion and the second portion of the at last one Schottky diode trench gate.

10. The method of claim 8, further comprising:

depositing the polysilicon comprises depositing a blanket polysilicon layer;

forming a patterned gate mask over the blanket polysilicon layer, and

etching the blanket polysilicon layer to form the at least one trench FET trench gate, the at least one Schottky diode trench gate, and at least one lateral FET gate.

11. The method of claim 10, further comprising:

etching the blanket polysilicon layer forms an upper surface of the at least one lateral FET gate, an upper surface of the at least one trench FET gate, and an upper surface of the at least one Schottky diode trench gate, wherein the upper surface of the at least one lateral FET gate is above the upper surface of the at least one trench FET gate and is above the upper surface of the at least one Schottky diode trench gate.

12. The method of claim 11, further comprising:

subsequent to etching the blanket polysilicon layer, etching the at least one Schottky diode trench gate such that an upper surface of the at least one trench FET gate is above an upper surface of the at least one Schottky diode trench gate.

13. A method used during the formation of a semiconductor device, comprising:

forming an epitaxial layer over a semiconductor substrate;

forming a patterned oxidation-resistant layer over the epitaxial layer;

forming a patterned buried layer mask over the patterned oxidation-resistant layer;

with the patterned buried layer mask and the patterned oxidation-resistant layer in place, performing a first dopant implant to implant a first dopant having a first conductivity type into the epitaxial layer, wherein the first dopant implant is blocked by both the patterned buried layer mask and the patterned oxidation-resistant layer;

with the patterned buried layer mask and the patterned oxidation-resistant layer in place, performing a second dopant implant to implant a second dopant having a second conductivity type different from the first conductive type into the epitaxial layer, wherein the second dopant implant is blocked by the patterned buried layer mask and passes through the patterned oxidation-resistant layer;

removing the patterned buried layer mask;

with the oxidation-resistant layer in place, oxidizing the epitaxial layer to form a field oxide layer; and

subsequent to oxidizing the epitaxial layer, removing the oxidation-resistant layer.

14. The method of claim 13, further comprising:

forming a trench mask over the field oxide layer;

etching the field oxide and the epitaxial layer using the trench mask as a pattern; and

performing a third dopant implant to implant a dopant into the epitaxial layer using the etched field oxide to block the third dopant implant.

15. The method of claim 14, further comprising:

forming at least a first opening and a second opening in the epitaxial layer during the etching of the epitaxial layer;

forming a conductive gate layer over the epitaxial layer and within the first opening and within the second opening in the epitaxial layer; and

etching the conductive gate layer to form a Schottky diode gate within the first opening and a trench field effect transistor (FET) gate within the second opening.

16. The method of claim 15, further comprising:

the etching of the conductive gate layer further forms a lateral FET gate over the epitaxial layer.

17. An electronic system, comprising:

a power supply;

a first voltage converter electrically coupled to the power supply with a first power bus and a second voltage converter electrically coupled to the power supply with the first power bus, wherein at least one of the first voltage converter and the second voltage converter comprises;

a first semiconductor die comprising;

a high-side transistor comprising a lateral field effect transistor (FET) and a source region for the lateral field effect transistor;

a low-side transistor comprising a trench FET, a drain region for the trench FET which is electrically coupled with the source region of the lateral FET, and a source region for the trench FET;

a trench guarded Schottky diode integrated into the semiconductor die, wherein an anode of the trench guarded Schottky diode is electrically coupled with the source region of the trench FET and a cathode of the trench guarded Schottky diode is electrically coupled with the drain region of the trench FET and the source region of the lateral FET; and

an output provided on the non-circuit side of the semiconductor die, wherein the trench guarded Schottky diode is integrated into a cell of the trench FET;

a second semiconductor die comprising a controller/voltage regulator adapted to control the first semiconductor die; and

a first data bus adapted to pass data between the first semiconductor die and the second semiconductor die;

at least one digital circuit die electrically coupled to the first voltage converter with a second power bus;

at least one memory device electrically coupled to the second voltage converter with a third power bus; and

a second data bus adapted to pass data between the processor and the at least one memory device.

18. The electronic system of claim 17, further comprising:

an upper surface of a trench gate of the trench FET is above an upper surface of a trench gate of the trench guarded Schottky diode.

19. The electronic system of claim 17, further comprising:

the source of the trench FET which is electrically coupled to a gate of the trench guarded Schottky diode through a metal layer.

20. The electronic system of claim 19, further comprising:

an upper surface of the gate of the trench guarded Schottky diode; and

a doped body region having an upper surface,

wherein the upper surface of the gate of the trench guarded Schottky diode is below the upper surface of the body region.

21. The electronic system of claim 17, further comprising:

a trench conductor which electrically couples the source of the lateral FET to a semiconductor substrate.

22. The electronic system of claim 17, further comprising:

a metal layer on the non-circuit side of the semiconductor die, wherein an output of the semiconductor device circuit stage is electrically coupled to the metal layer.

23. The electronic system of claim 17, wherein the digital circuit die is a processor.