VOLTAGE CONVERTER WITH INTEGRATED SCHOTTKY DEVICE AND SYSTEMS INCLUDING SAME

• US 20110156682A1
• Filed: 10/05/2010
• Published: 06/30/2011
• Est. Priority Date: 12/30/2009
• Status: Abandoned Application

• Current Assignee: Intersil Americas LLC (Renesas Electronics Corporation)
• Original Assignee: Intersil Americas LLC (Renesas Electronics Corporation)
• Inventors: Hebert, Francois, Girdhar, Dev Alok
• Application Number:
  US12/898,664
• Publication Number:
  US 20110156682A1
• Time in Patent Office: Days
• US Class Current: 323/283
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48464 the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
• CPC Class Codes: H01L 24/29 of an individual layer connector
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/4175 for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/47 Schottky barrier electrodes H01L29/435 takes precedence
• CPC Class Codes: H01L 29/66143 Schottky diodes
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/872 : Schottky diodes
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/0781 : being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/12036 : PN diode
• CPC Class Codes: H01L 2924/13062 : Junction field-effect transistor [JFET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A semiconductor device such as a voltage converter includes a circuit stage such as an output stage having a high side device and a low side device which can be formed on a single die (i.e., a “PowerDie”) and connected to each other through a semiconductor substrate, and further includes a Schottky diode integrated with at least one of the low side device and the high side device. Both the high side device and the low side device can include lateral diffused metal oxide semiconductor (LDMOS) transistors. Because both output transistors include the same type of transistors, the two devices can be formed simultaneously, thereby reducing the number of photomasks over other voltage converter designs. The voltage converter can further include a controller circuit on a different die which can be electrically coupled to, and co-packaged with, the PowerDie. Various embodiments of the Schottky diode can provide Schottky protection and, additionally JFET protection for the Schottky device.

Claims

1. A semiconductor device circuit stage, comprising:

a semiconductor die comprising at least one semiconductor layer, a circuit side and a non-circuit side;

a high side lateral diffusion metal oxide semiconductor (LDMOS) field effect transistor (FET) on the circuit side of the semiconductor die;

a source region and a drain region of the high side LDMOS FET;

a low side LDMOS FET on the circuit side of the semiconductor die;

a source region of the low side LDMOS FET within the semiconductor layer;

a drain region of the low side LDMOS FET, wherein the drain region of the low side LDMOS FET is electrically coupled with the source region of the high side LDMOS FET;

a body region of the low side LDMOS FET within the semiconductor layer;

an output node electrically coupled with the source region of the high side LDMOS FET and the drain region of the low side LDMOS FET;

a conductive layer over the semiconductor layer which is electrically coupled with the body region of the low side LDMOS FET and with the source region of the low side LDMOS FET; and

at least one Schottky diode including contact between the conductive layer and a doped region of the semiconductor layer.

2. The semiconductor device circuit stage of claim 1, further comprising:

the body region of the low side LDMOS FET comprises a net first-type conductivity;

the doped region of the semiconductor layer comprises a net second-type conductivity which is opposite to the first type conductivity; and

a junction between the body region of the low side LDMOS FET and the doped region of the semiconductor layer which provides junction FET (JFET) protection for the Schottky diode.

3. The semiconductor device circuit stage of claim 2, further comprising:

a buried layer of the low side LDMOS FET;

the buried layer is doped to the net first-type conductivity;

the body region is within the buried layer; and

an edge of the body region is generally aligned with an edge of the buried layer.

4. The semiconductor device circuit stage of claim 3, wherein the buried layer is a first buried layer and the body region is a first body region, further comprising:

a second buried layer spaced from the first buried layer by the doped region of the semiconductor layer; and

a second body region spaced from the first body region by the doped region of the semiconductor layer.

5. The semiconductor device circuit stage of claim 2, wherein the body region is a first body region, further comprising:

a second body region spaced from the first body region by the doped region of the semiconductor layer.

6. The semiconductor device circuit stage of claim 2, further comprising:

a buried layer of the low side LDMOS FET;

the buried layer is doped to the net first-type conductivity;

a portion of the body region is within the buried layer; and

an end of the body region extends beyond an end of the buried layer.

7. The semiconductor device circuit stage of claim 2, further comprising:

a buried layer of the low side LDMOS FET;

the body region is nested within the buried layer.

8. The semiconductor device circuit stage of claim 1, further comprising:

a buried layer of the low side LDMOS FET comprising a net first-type conductivity;

the body region of the low side LDMOS FET comprises the net first-type conductivity;

the doped region of the semiconductor layer comprises a net second-type conductivity which is opposite to the first type conductivity; and

the Schottky diode is free from a region of the net first-type conductivity.

9. The semiconductor device circuit stage of claim 1, wherein the conductive layer further comprises a trench conductor within a trench in the semiconductor layer.

10. The semiconductor device circuit stage of claim 9, wherein the trench conductor comprises a silicide layer and a metal layer.

11. The semiconductor device circuit stage of claim 9, further comprising:

a tuning implant within the semiconductor layer electrically coupled with the trench conductor.

12. The semiconductor device circuit stage of claim 1, further comprising:

a lead frame first lead electrically coupled with the source region of the low side LDMOS FET;

a lead frame second lead electrically coupled with the drain region of the high side LDMOS FET; and

a lead frame third lead electrically coupled with the non-circuit side of the semiconductor die.

13. The semiconductor device circuit stage of claim 12, wherein, during operation of the semiconductor device circuit stage:

the lead frame first lead is electrically coupled with device ground; and

the lead frame second lead is electrically coupled with device voltage in.

14. A semiconductor device circuit stage, comprising:

a semiconductor die, comprising;

a single semiconductor substrate comprising at least one semiconductor layer;

a low side transistor over the single semiconductor substrate and comprising a source region within the semiconductor layer, a drain region within the semiconductor layer, a body region within the semiconductor layer, and a transistor gate;

a high side transistor over the single semiconductor substrate and comprising a source region within the semiconductor layer, a drain region within the semiconductor layer, and a transistor gate;

a first conductive structure within the semiconductor die and interposed between the drain region of the low side transistor and the source region of the high side transistor, wherein the conductive structure is electrically coupled with the semiconductor substrate, with the drain region of the low side transistor, and with the source region of the high side transistor;

the drain region of the low side transistor is electrically coupled to the source region of the high side transistor through at least the first conductive structure;

the drain region of the high side transistor is electrically connected to a device voltage in (V_IN) pinout;

the source region of the low side transistor is electrically connected to a device ground (P_GND) pinout; and

a second conductive structure within the semiconductor die which electrically couples the body region of the low side transistor to the source region of the low side transistor; and

at least one Schottky diode including contact between the second conductive structure and the semiconductor layer.

15. The semiconductor device circuit stage of claim 14, further comprising:

the body region of the low side transistor is doped to a net first-type conductivity;

the semiconductor layer comprises a region doped to a net second-type conductivity which is opposite to the first type conductivity; and

a junction between the body region of the low side transistor and the semiconductor layer region doped to the net second type conductivity which provides junction FET (JFET) protection for the Schottky diode.

16. The semiconductor device circuit stage of claim 15, further comprising:

a buried layer of the low side transistor;

the buried layer is doped to the net first-type conductivity;

the body region is within the buried layer; and

an edge of the body region is generally aligned with an edge of the buried layer.

17. The semiconductor device circuit stage of claim 15, further comprising:

a buried layer of the low side transistor;

the buried layer is doped to the net first-type conductivity;

a portion of the body region is within the buried layer; and

an end of the body region extends beyond an end of the buried layer.

18. An electronic system comprising:

a voltage converter, comprising;

a first semiconductor die comprising voltage converter controller circuitry;

a second semiconductor die comprising at least one semiconductor layer, a circuit side and a non-circuit side;

a high side lateral diffusion metal oxide semiconductor (LDMOS) field effect transistor (FET) on the circuit side of the second semiconductor die;

a source region of the high side LDMOS FET;

a low side LDMOS FET on the circuit side of the second semiconductor die;

a drain region of the low side LDMOS FET electrically coupled with the source region of the high side LDMOS FET;

a source region of the low side LDMOS FET within the semiconductor layer;

a body region of the low side LDMOS FET within the semiconductor layer;

an output node of the circuit stage electrically coupled with the source region of the high side LDMOS FET and the drain region of the low side LDMOS FET;

a conductive layer over the semiconductor layer which is electrically coupled with the body region of the low side LDMOS FET and with the source region of the low side LDMOS FET; and

at least one Schottky diode including contact between the conductive layer and the semiconductor layer;

a power source which powers the voltage converter device through a first power bus;

a processor electrically coupled to the voltage converter device through a second power bus; and

memory coupled to the processor through a data bus.

19. A method for forming a semiconductor device circuit stage, comprising:

forming a conductive layer over a semiconductor substrate of a semiconductor die, wherein;

forming the conductive layer electrically couples a source region of a low side lateral diffusion metal oxide semiconductor (LDMOS) field effect transistor (FET) to a body region of the LDMOS FET, and

forming the conductive layer electrically contacts the conductive layer with a doped region of the semiconductor substrate, wherein a Schottky diode includes the electrical contact between the conductive layer and the doped region of the semiconductor substrate;

electrically coupling a drain region of the low side LDMOS FET with a source region of a high side LDMOS FET;

electrically coupling the source region of the low side LDMOS FET with a device ground pinout; and

electrically coupling a drain region of a high side LDMOS FET with a device voltage in pinout.

20. A method for forming a semiconductor device circuit stage, comprising:

implanting a source region for a low side transistor into a single semiconductor substrate;

implanting a drain region for the low side transistor into the single semiconductor substrate;

implanting a body region for the low side transistor into the single semiconductor substrate; and

etching a gate layer to form a low side transistor gate over the single semiconductor substrate;

implanting a source region for a high side transistor into the single semiconductor substrate;

implanting a drain region for the high side transistor into the single semiconductor substrate; and

etching the gate layer to form a high side transistor gate over the single semiconductor substrate;

forming a conductive structure between the low side transistor drain region and the high side transistor source region, wherein the conductive structure is electrically coupled to the single semiconductor substrate through contact between the conductive structure and the single semiconductor substrate;

forming a first conductive layer which electrically couples the conductive structure to the drain region of the low side transistor;

forming a second conductive layer which electrically couples the drain region of the low side transistor to the source region of the high side transistor; and

forming a third conductive layer over the single semiconductor layer which electrically couples the body region of the low side transistor to the source region of the low side transistor,

wherein at least one Schottky diode includes contact between the third conductive layer and the single semiconductor substrate.

21. The method of claim 20, further comprising:

implanting the body region of the low side transistor to a net first-type conductivity; and

implanting a region of the semiconductor layer to a net second-type conductivity which is opposite to the first type conductivity, wherein

a junction between the body region of the low side transistor and the region of the semiconductor layer doped to the net second type conductivity which provides junction FET (JFET) protection for the Schottky diode.

22. The method of claim 21, further comprising:

implanting a buried layer of the low side transistor into the semiconductor layer to the net first-type conductivity;

the implanting of the body region forms the body region within the buried layer; and

diffusing the buried layer and the body region such that, subsequent to the diffusion, an edge of the body region is generally aligned with an edge of the buried layer.

23. The method of claim 22, further comprising:

implanting a buried layer of the low side transistor to the net first-type conductivity;

the implanting of the body region forms a portion of the body region within the buried layer; and

the implanting of the body region forms an end of the body region which extends beyond an end of the buried layer.

24. The method of claim 20, further comprising:

electrically coupling a lead frame first lead to the source region of the low side LDMOS FET;

electrically coupling a lead frame second lead to the drain region of the high side LDMOS FET; and

attaching the non-circuit side of the semiconductor die to a lead frame die pad to electrically couple an output of the circuit stage to a lead frame third lead.

25. The method of claim 20, further comprising:

forming the conductive structure between the low side transistor drain region and the high side transistor source region comprises implanting a sinker region into the single semiconductor substrate

26. The method of claim 20, further comprising:

forming the conductive structure between the low side transistor drain region and the high side transistor source region comprises etching a trench into the single semiconductor substrate and forming a trench conductor within the trench.

27. A method for forming a semiconductor device circuit stage, comprising:

forming a low side transistor using a method comprising;

implanting a source region for the low side transistor into a single semiconductor substrate;

implanting a drain region for the low side transistor into the single semiconductor substrate;

implanting a body region for the low side transistor into the single semiconductor substrate; and

etching a gate layer to form a low side transistor gate over the single semiconductor substrate;

forming a high side transistor using a method comprising;

implanting a source region for the high side transistor into the single semiconductor substrate;

implanting a drain region for the high side transistor into the single semiconductor substrate; and

etching the gate layer to form a high side transistor gate over the single semiconductor substrate;

forming a conductive structure between the low side transistor drain region and the high side transistor source region using a method comprising one of;

implanting a sinker region into the single semiconductor substrate;

or

etching a trench into the single semiconductor substrate and forming a trench conductor within the trench,

wherein the conductive structure is electrically coupled to the single semiconductor substrate through contact between the conductive structure and the single semiconductor substrate;

forming a first conductive layer which electrically couples the conductive structure to the drain region of the low side transistor;

forming a second conductive layer which electrically couples the drain region of the low side transistor to the source region of the high side transistor;

etching into the single semiconductor substrate and through the source region of the low side transistor;

etching into the single semiconductor substrate and into the body region of the low side transistor to form a Schottky diode trench in the single semiconductor substrate; and

forming a Schottky diode trench conductor within the Schottky diode trench, wherein the Schottky diode trench conductor electrically couples the body region of the low side transistor to the source region of the low side transistor,

wherein at least one Schottky diode includes contact between the third conductive layer and the single semiconductor substrate.