WAFER TEST CASSETTE SYSTEM

• US 20110156735A1
• Filed: 12/27/2010
• Published: 06/30/2011
• Est. Priority Date: 12/31/2009
• Status: Active Grant

• Current Assignee: FormFactor Incorporated
• Original Assignee: FormFactor Incorporated
• Inventors: Breinlinger, Keith J., Hobbs, Eric D.
• Granted Patent: US 8,872,532 B2
• Time in Patent Office: Days
• US Class Current: 324/750.19
• CPC Class Codes: G01R 1/0491 for testing integrated circuits on wafers, e.g. wafer-level test cartridge
• CPC Class Codes: G01R 31/3025 Wireless interface with the DUT

Abstract

Wafer cassette systems and methods of using wafer cassette systems. A wafer cassette system can include a base and a probe card assembly. The base and the probe card assembly can each include complementary interlocking alignment elements. The alignment elements can constrain relative movement of the base and probe card assembly in directions parallel to a wafer receiving surface of the base, while permitting relative movement in a direction perpendicular to the receiving surface.

Claims

1. A wafer cassette system for holding a wafer comprising:

a base comprising a fiducial, a receiving surface sized to receive said wafer, and a plurality of first alignment elements;

a probe card assembly comprising a substrate, a plurality of probes disposed on a surface of said substrate and arranged to contact terminals of said wafer, and a plurality of second alignment elements corresponding to said first alignment elements; and

wherein said first alignment elements and said second alignment elements comprise complementary shapes capable of interlocking to constrain relative movement of said base and said probe card assembly in directions substantially parallel to said receiving surface while permitting relative movement of said base and said probe card assembly in a direction substantially perpendicular to said receiving surface.

2. The system of claim 1, wherein said first alignment elements and said second alignment elements are capable of interlocking to define a predefined relative position of said base and said probe card assembly constrained in two degrees of translation and three degrees of rotation and enabling translation in a third degree of translation.

3. The system of claim 1, further comprising a vacuum seal disposed to seal space between said base and said probe card assembly.

4. The system of claim 1, wherein one of said base and said probe card assembly comprises a compression stop disposed to define a limit to relative movement of said base and said probe card assembly toward each other.

5. The system of claim 4, wherein said compression stop has an adjustable height.

6. The system of claim 1, wherein one of said first alignment element and said second alignment element comprises a protrusion, and another of said first alignment element and said second alignment element comprises a thermocentric slot.

7. The system of claim 1, wherein the first alignment element and the second alignment element comprise a kinematic coupling in series with a motion guidance mechanism.

8. The system of claim 7, wherein the motion guidance mechanism comprises a flexure.

9. The system of claim 1, wherein one of said first alignment element and said second alignment element comprises a protrusion, and another of said first alignment element and said second alignment element comprises a flexure.

10. The system of claim 1, further comprising a latching mechanism disposed to enable locking said base and said probe card assembly together.

11. The system of claim 1, wherein said first alignment elements and said second alignment elements provide a wiping motion of said probes relative to said terminals.

12. A method of providing electrical contacts to terminals disposed on a wafer comprising:

positioning said wafer onto a receiving surface of a base in a predefined position relative to a fiducial disposed on said base;

coupling said base to a probe card assembly, wherein said probe card assembly comprises a plurality of probes disposed on a substrate of said probe card assembly, and wherein a plurality of first alignment elements disposed on said base interlock with a corresponding plurality of second alignment elements disposed on said probe card assembly to constrain relative position of said receiving surface and said probe card assembly in directions parallel to said receiving surface;

moving said base relative to said probing assembly in a direction perpendicular to said receiving surface while constrained by said first alignment elements and said second alignment elements to bring ones of said probes into contact with corresponding ones of said terminals to form temporary pressure based electrical connections.

13. The method of claim 12, wherein said moving comprises constraining rotation of said base relative to said probe assembly, constraining translation of said base relative to said probe assembly in a first direction and a second direction, and permitting translation of said base in a third direction.

14. The method of claim 12, where said moving comprises:

performing overtravel to create contact force between said ones of said probes and said corresponding ones of said terminals; and

generating scrubbing motion of said ones of said probes across corresponding ones of said terminals.

15. The method of claim 12, wherein said coupling comprises inserting a protrusion disposed on one of said probe card assembly and said base into a corresponding receptacle disposed on an other of said probe card assembly and said base.

16. The method of claim 12, further comprising creating a vacuum in an area between said base and said probe card assembly.

17. The method of claim 12, further comprising changing a temperature of said base and said wafer before said coupling.

18. The method of claim 12, further comprising changing a temperature of said base and said wafer to a first temperature wherein said probe card assembly is at a second temperature, and wherein a thermal strain of said wafer at said first temperature matches a thermal strain of said probe card assembly at said second temperature.

19. The method of claim 12, further comprising adjusting a height of a compression stop disposed on one of said base and said probe card assembly according to a nominal height of said wafer so that said moving produces a predefined overtravel.

20. A method of testing a plurality of wafers simultaneously, the method comprising:

obtaining a tester unit, said tester unit comprising a plurality of probe card assemblies, each probe card assembly comprising a plurality of probes and a plurality of first elements, and wherein said probe card assemblies are electrically connected to a test subsystem;

loading a plurality of wafers into said tester unit, wherein loading each one of said plurality of wafers comprises;

positioning said one wafer onto a horizontal surface of a corresponding one of a plurality of bases in a predefined position relative to a fiducial disposed on said corresponding base, wherein said corresponding base comprises a plurality of second alignment elements;

moving said corresponding base into position proximate to said corresponding probe card assembly to interlock said second alignment elements of said corresponding base into said first alignment elements of said corresponding probe card assembly;

translating said corresponding base relative to said corresponding probe card assembly in a vertical direction while constrained in horizontal directions by said first alignment elements and said second alignment elements to make temporary pressure based electrical contact between said probes of said corresponding probe card assembly and said terminals of said one wafer; and

testing said plurality of wafers using said test subsystem.

21. The method of claim 20, wherein said loading further comprises changing a temperature of said corresponding base and said one wafer after said positioning and before said moving.

22. The method of claim 20, wherein said loading further comprises creating a vacuum in an area between said corresponding base and said corresponding probe card assembly.

23. The method of claim 20, wherein said testing comprises performing a burn-in test on said plurality of wafers.