SIGNAL MONITORING SYSTEMS

• US 20110156758A1
• Filed: 12/29/2009
• Published: 06/30/2011
• Est. Priority Date: 12/29/2009
• Status: Active Grant

• Current Assignee: O2 Micro International Limited (O2 Micro Incorporated)
• Original Assignee: O2 Micro International Limited (O2 Micro Incorporated)
• Inventors: LIU, Shiqiang, HU, Juncai, LIU, Quanwang, LI, Guoxing
• Granted Patent: US 8,030,973 B2
• Time in Patent Office: Days
• US Class Current: 327/72
• CPC Class Codes: G01R 19/0084 measuring voltage only all subgroups of G01R19/00 take precedence
• CPC Class Codes: G01R 31/396 Acquisition or processing of data for testing or for monitoring individual cells or groups of cells within a battery
• CPC Class Codes: G01R 35/005 Calibrating; Standards or reference devices, e.g. voltage or resistance standards, "golden" references G01R33/0035, G01R35/002 take precedence

Abstract

In a signal monitoring system, a circuit includes an input terminal and an output terminal. In addition, a processor coupled to the circuit is operable for calculating a parameter indicative of an error factor of the circuit by setting a level difference between an input signal at the input terminal and an output signal at the output terminal to a predetermined level.

Claims

1. A system comprising:

a circuit comprising a first input terminal and a first output terminal, and

a processor coupled to said circuit and operable for calculating a parameter indicative of an error factor of said circuit by setting a level difference between a first input signal at said first input terminal and a first output signal at said first output terminal to a first predetermined level.

2. The system as claimed in claim 1, wherein said processor calculates said parameter by setting a level difference between said first input signal and a second input signal at a second input terminal of said circuit to a second predetermined level.

3. The system as claimed in claim 1, wherein said processor calculates a real-time level difference between said first input signal and a second input signal at a second input terminal of said circuit according to said parameter, and according to a real-time level difference between said first output signal and a second output signal at a second output terminal of said circuit.

4. The system as claimed in claim 1, wherein said circuit comprises an operational amplifier coupled to said first input terminal via a first resistor, coupled to a second output terminal of said circuit via a second resistor, coupled to a second input terminal of said circuit via a third resistor, and coupled to said first output terminal via a fourth resistor.

5. The system as claimed in claim 1, wherein said error factor comprises an input voltage offset of said operational amplifier.

6. The system as claimed in claim 1, wherein a value of said parameter varies as an ambient condition varies.

7. The system as claimed in claim 1, wherein a voltage level difference between said first output terminal and a second output terminal of said circuit is given by V_OUT2−

V_OUT1=(V_IN2−

V_IN1)*K4+(V_IN1−

V_OUT1)*K₅−

V_OS/K₁, where V_OUT1 represents a voltage level at said first output terminal, V_OUT2 represents a voltage level at a second output terminal of said circuit, V_IN1 represents a voltage level at said first input terminal, V_IN2 represents a voltage level at a second input terminal of said circuit, V_OS represents a voltage offset of said circuit, K₁ represents a first resistance ratio of said circuit, K₄ represents a second resistance ratio of said circuit, and K₅ represents a third resistance ratio of said circuit.

8. The system as claimed in claim 1, further comprising:

an analog-to-digital converter coupled to said circuit and operable for providing a digital signal to said processor, wherein said digital signal indicates a level difference between said first output signal and a second output signal at a second output terminal of said circuit.

9. The system as claimed in claim 1, further comprising:

a multiplexer operable for providing a selected signal that is selected from a reference signal and a plurality of real-time input signals to a second input terminal of said circuit.

10. The system as claimed in claim 9, wherein said multiplexer comprises a plurality of switches coupled to a plurality of cells, wherein each real-time input signal of said plurality of real-time input signals is a voltage level at a terminal of a corresponding cell of said plurality of cells.

11. A method comprising:

setting a level difference between a first input signal at a first input terminal of a circuit and a first output signal at a first output terminal of said circuit to a first predetermined level; and

calculating a parameter indicative of an error factor of said circuit based on said first predetermined level.

12. The method as claimed in claim 11, further comprising:

setting a level difference between said first input signal and a second input signal at a second input terminal of said circuit to a second predetermined level; and

calculating said parameter based on said second predetermined level.

13. The method as claimed in claim 11, further comprising:

calculating a real-time level difference between said first input signal and a second input signal at a second input terminal of said circuit according to said parameter, and according to a real-time level difference between said first output signal and a second output signal at a second output terminal of said circuit.

14. The method as claimed in claim 11, wherein a value of said parameter varies as an ambient condition varies.

15. The method as claimed in claim 11, wherein a voltage level difference between said first output terminal and a second output terminal of said circuit is given by V_OUT2−

V_OUT1=(V_IN2−

V_IN1)*K₄+(V_IN1−

V_OUT1)*K₅−

V_OS/K₁, where V_OUT1 represents a voltage level at said first output terminal, V_OUT2 represents a voltage level at a second output terminal of said circuit, V_IN1 represents a voltage level at said first input terminal, V_IN2 represents a voltage level at a second input terminal of said circuit, V_OS represents a voltage offset of a circuit, K₁ represents a first resistance ratio of said circuit, K₄ represents a second resistance ratio of said circuit, and K₅ represents a third resistance ratio of said circuit.

16. The method as claimed in claim 11, further comprising:

selecting a selected signal from a reference signal and a plurality of real-time input signals; and

providing said selected signal to a second input terminal of said circuit.

17. A system comprising:

a circuit comprising a first input terminal, a second input terminal, and a first output terminal, and operable for selectively receiving a first voltage level at a first detect terminal via said first input terminal, and operable for selectively receiving a second voltage level at a second detect terminal via said second input terminal; and

a processor operable for determining an error factor of said circuit by setting a voltage level difference between said first input terminal and said first output terminal to a first predetermined level, and operable for calculating a difference between said first and second voltage levels.

18. The system as claimed in claim 17, wherein said processor determines said error factor by setting a voltage level difference between said first input terminal and said second input terminal to a second predetermined level.

19. The system as claimed in claim 17, wherein said circuit comprises an operational amplifier coupled to said first input terminal via a first resistor, coupled to a second output terminal of said circuit via a second resistor, coupled to said second input terminal via a third resistor, and coupled to said first output terminal via a fourth resistor.

20. The system as claimed in claim 17, wherein said error factor is determined based on a relationship between four voltage levels respectively at said first input terminal, said second input terminal, said first output terminal, and a second output terminal of said circuit.

21. The system as claimed in claim 17, wherein said error factor varies as an ambient condition varies.

22. The system as claimed in claim 17, wherein a voltage level difference between said first output terminal and a second output terminal of said circuit is given by V_OUT2−

V_OUT1=(V_IN2−

V_IN1)*K₄+(V_IN1−

V_OUT1)*K₅−

V_OS/K₁, where V_OUT1 represents a voltage level at said first output terminal, V_OUT2 represents a voltage level at said second output terminal, V_IN1 represents a voltage level at said first input terminal, V_IN2 represents a voltage level at said second input terminal, V_OS represents a voltage offset of said circuit, K₁ represents a first resistance ratio of said circuit, K₄ represents a second resistance ratio of said circuit, and K₅ represents a third resistance ratio of said circuit.

23. The system as claimed in claim 17, further comprising:

an analog-to-digital converter coupled to said circuit and operable for providing a digital signal to said processor, wherein said digital signal indicates a voltage level difference between said first output terminal and a second output terminal of said circuit.

24. The system as claimed in claim 17, further comprising:

a multiplexer operable for providing a selected signal that is selected from a reference signal and said second voltage level to said second input terminal.