DIGITAL PHASE LOCKED LOOP

• US 20110156783A1
• Filed: 12/23/2010
• Published: 06/30/2011
• Est. Priority Date: 12/24/2009
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: PAVLOVIC, Nenad, BERGERVOET, Jozef Reinerus Maria
• Granted Patent: US 8,362,815 B2
• Time in Patent Office: Days
• US Class Current: 327/159
• CPC Class Codes: H03L 7/081 provided with an additional controlled phase shifter H03L7/0998 takes precedence
• CPC Class Codes: H03L 7/0991 the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider H03L7/0995 takes precedence; fixed oscillators with means for selecting among various phases H03L7/0814
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence

Abstract

A digital phase locked loop (300) configured to receive a reference clock signal (302) and a channel control word (308), and to generate an output clock signal (304). The digital phase locked loop comprising an adjustable delay component (306) configured to: receive the reference clock signal (302), apply a time delay to the reference clock signal (302) in accordance with a time delay control signal (316); and provide a delayed reference clock signal (318). The digital phase locked loop further comprising a timing component (320) configured to process the delayed reference clock signal (318) and the output clock signal (304), and generate a first control signal (322) representative of the phase of the output clock signal (304); a reference accumulator (310) configured to receive the channel command word (308) and generate: a second control signal (312) representative of the phase of an intended output clock signal; and the time delay control signal (316) such that the delayed reference clock signal (318) is delayed by a period of time representative of a first portion of the phase of the intended output clock signal. The digital phase locked loop also comprising a controller (314) configured to process the first and second control signals (322, 312), and generate a DCO control signal (326) for setting the frequency of a digitally controlled oscillator (328) in accordance with the first and second control signals (322, 312); and a digitally controlled oscillator (328) configured to generate the output clock signal (304) in accordance with the DCO control signal (326).

Claims

1. A digital phase locked loop configured to receive a reference clock signal and a channel control word, and to generate an output clock signal, the digital phase locked loop comprising:

an adjustable delay component configured to;

receive the reference clock signal,

apply a time delay to the reference clock signal in accordance with a time delay control signal; and

provide a delayed reference clock signal;

a timing component configured to process the delayed reference clock signal and the output clock signal, and generate a first control signal representative of a phase of the output clock signal;

a reference accumulator configured to receive the channel command word and generate;

a second control signal representative of the phase of an intended output clock signal; and

the time delay control signal such that the delayed reference clock signal is delayed by a period of time representative of a first portion of the phase of the intended output clock signal;

a controller configured to process the first and second control signals, and generate a DCO control signal for setting a frequency of a digitally controlled oscillator in accordance with the first and second control signals; and

a digitally controlled oscillator configured to generate the output clock signal in accordance with the DCO control signal.

2. The digital phase locked loop of claim 1, wherein the first portion of the intended output clock signal represents a value that is less than the quantisation magnitude of the timing component.

3. The digital phase locked loop of claim 1, wherein the digital phase locked loop is a fractional-N phase locked loop.

4. The digital phase locked loop of claim 1, wherein the first portion of the intended output clock signal represents a fractional portion of the intended output clock signal, and the timing component is configured to generate the first control signal in accordance with its quantisation magnitude, which is representative of an integer portion of the intended output clock signal.

5. The digital phase locked loop of claim 1, wherein the adjustable delay component is a digital to time converter, and, optionally, is a Vernier digital to time converter.

6. The digital phase locked loop of claim 1, wherein the first control signal is representative of whether the phase of the output clock signal precedes or succeeds the delayed reference clock signal.

7. The digital phase locked loop of claim 1, wherein the timing component is a counter.

8. The digital phase locked loop of claim 1, wherein the digital phase locked loop is configured to operate as a bang-bang phase locked loop.

9. The digital phase locked loop of claim 1, wherein the adjustable delay component is configured to apply dynamic element matching.

10. The digital phase locked loop of claim 1, further comprising a digital filter configured to filter the DCO control signal in order to provide a time-averaged value of the DCO control signal for setting the frequency of the DCO.

11. The digital phase locked loop of claim 1, further comprising a processor configured to receive the second control signal and generate a quantisation error signal representative of the quantisation error of the adjustable delay component, and wherein the controller is further configured to process the quantisation error signal in order to generate the DCO control signal.

12. The digital phase locked loop of claim 1, further comprising a processor configured to perform a spectral analysis of the DCO control signal in order to determine an average unit element delay of the adjustable delay component, and generate a calibrated time delay control signal in accordance with the channel control word and the determined average unit element delay.

13. The digital phase locked loop of claim 1, wherein the controller is a probabilistic phase detector, and wherein at least one parameter of the probabilistic phase detector can be calibrated in accordance with at least one operational characteristic of the digital phase locked loop.

14. The digital phase locked loop of claim 1, wherein the at least one parameter of the probabilistic phase detector include at least one of a jitter level and/or distribution in the digital phase locked loop.

15. A computer program, which when run on a computer, causes the computer to configure the digital phase locked loop of claim 1.

16. The digital phase locked loop of claim 13, wherein the operational characteristic includes at least one of phase error and quantization error of the DTC.