FLIP-FLOP CIRCUIT AND FREQUENCY DIVIDING CIRCUIT

• US 20110156786A1
• Filed: 09/14/2010
• Published: 06/30/2011
• Est. Priority Date: 12/24/2009
• Status: Abandoned Application

• Current Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: Yamaguchi, Satoshi
• Application Number:
  US12/881,436
• Publication Number:
  US 20110156786A1
• Time in Patent Office: Days
• US Class Current: 327/203
• CPC Class Codes: H03K 23/662 by adding or suppressing pulses
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 3/356139 with synchronous operation
• CPC Class Codes: H03K 3/35625 using complementary field-effect transistors

Abstract

A flip-flop circuit has a function of respectively switching ON/OFF state of operation of a first data retaining circuit in a master side element and a second data retaining circuit in a slave side element, i.e., constituent elements of the flip-flop circuit, wherein the flip-flop circuit performs timing control, so as to reduce unnecessary current, eliminate the affect caused by parasitic capacitance. The flip-flop circuit operates with a low power consumption but has a high maximum operating frequency.

Claims

1. A flip-flop circuit comprising a master side element including a first data reading circuit and a first data retaining circuit, and a slave side element including a second data reading circuit and a second data retaining circuit,

wherein power supplies of the first data retaining circuit and the second data reading circuit are controlled by a normal phase clock signal input from an outside, and power supplies of the first data reading circuit and the second data retaining circuit are controlled by a reversed phase clock signal having a phase opposite to the normal phase clock signal, wherein the first data reading circuit includes a differential circuit, and wherein the first data retaining circuit, the second data reading circuit, and the second data retaining circuit include inverter circuits.

2. The flip-flop circuit according to claim 1, wherein the first data retaining circuit includes a first NMOS, and an input end and an output end of a first inverter are interconnected with an output end and an input end of a second inverter, wherein an earthing end of the first inverter and the second inverter is connected to a low potential side power supply via the first NMOS, and wherein a power supply end of the first inverter and the second inverter is connected to a high potential side power supply.

3. The flip-flop circuit according to claim 2, wherein the first data reading circuit includes a first PMOS, a second PMOS, a second NMOS, a third NMOS, and a fourth NMOS,

wherein an input end of the first inverter in the first data retaining circuit is connected to the high potential side power supply via the first PMOS, and is connected to the low potential side power supply via the second NMOS and the third NMOS,

and wherein an input end of the second inverter in the first data retaining circuit is connected to the high potential side power supply via the second PMOS, and is connected to the low potential side power supply via the fourth NMOS and the third NMOS.

4. The flip-flop circuit according to claim 3, wherein the second data retaining circuit includes a fifth NMOS, and an input end and an output end of a third inverter are interconnected with an output end and an input end of a fourth inverter, wherein an earthing end of the third inverter and the fourth inverter is connected to a low potential side power supply via the fifth NMOS, and wherein a power supply end of each of the third inverter and the fourth inverter is connected to the high potential side power supply.

5. The flip-flop circuit according to claim 4, wherein the second data reading circuit includes a third PMOS, a fourth PMOS, a sixth NMOS, a seventh NMOS, and a eighth NMOS,

wherein an input end of the third inverter in the second data retaining circuit is connected to the high potential side power supply via the fourth PMOS, and is connected to the low potential side power supply via the eighth NMOS and the seventh NMOS,

wherein an input end of the fourth inverter in the second data retaining circuit is connected to the high potential side power supply via the third PMOS, and is connected to the low potential side power supply via the sixth NMOS and the seventh NMOS,

wherein an output end of the first inverter, i.e., one of output ends of the master side element, is connected to a gate terminal of the eighth NMOS, i.e., one of input ends of the slave side element,

and wherein an output end of the second inverter, i.e., the other of output ends of the master side element, is connected to a gate terminal of the sixth NMOS, i.e., the other of input ends of the slave side element.

6. The flip-flop circuit according to claim 4, wherein the second data reading circuit includes a fifth inverter, a sixth inverter, and a seventh NMOS,

wherein an input end of the third inverter in the second data retaining circuit is connected to an output end of the fifth inverter, and an input end of the fourth inverter in the second data retaining circuit is connected to an output end of the sixth inverter,

and wherein an earthing end of each of the fifth inverter and the sixth inverter is connected to the low potential side power supply via the seventh NMOS, and a power supply end of the fifth inverter and the sixth inverter is connected to the high potential side power supply.

7. The flip-flop circuit according to claim 5, wherein the normal phase clock signal is input to a gate terminal of each of the first PMOS, the second PMOS, the first NMOS, and the seventh NMOS, and a reversed phase clock signal having a phase opposite to the normal phase clock signal is input to a gate terminal of each of the third PMOS, the fourth PMOS, the third NMOS, and the fifth NMOS.

8. The flip-flop circuit according to claim 6, wherein the normal phase clock signal is input to a gate terminal of each of the first PMOS, the second PMOS, the first NMOS, and the seventh NMOS, and a reversed phase clock signal having a phase opposite to the normal phase clock signal is input to a gate terminal of each of the third NMOS and the fifth NMOS.

9. The flip-flop circuit according to claim 7, wherein the input terminal for inputting the normal phase data signal is the gate terminal of the second NMOS, and the input terminal for inputting the reversed phase data signal having a phase opposite to the normal phase data signal is the gate terminal of the fourth NMOS,

and wherein in the output terminal of the flip-flop circuit, an output end of the third inverter is a normal phase output signal terminal for outputting the normal phase output signal, and an output end of the fourth inverter is a reversed phase output terminal for outputting the reversed phase output signal having a phase opposite to the normal phase output signal.

10. The flip-flop circuit according to claim 8, wherein the input terminal for inputting the normal phase data signal is the gate terminal of the second NMOS, and the input terminal for inputting the reversed phase data signal having a phase opposite to the normal phase data signal is the gate terminal of the fourth NMOS,

and wherein in the output terminal of the flip-flop circuit, an output end of the third inverter is a normal phase output signal terminal for outputting the normal phase output signal, and an output end of the fourth inverter is a reversed phase output terminal for outputting the reversed phase output signal having a phase opposite to the normal phase output signal.

11. The flip-flop circuit according to claim 7, wherein the master side element and the slave side element further comprising reset devices,

wherein the reset devices comprises:

a first reset circuit arranged between the high potential side power supply and the output end of the second inverter, i.e., the output end of the master side element;

a second reset circuit in which a drain terminal and a source terminal of the first NMOS are respectively connected to a drain terminal and a source terminal of the second reset circuit in first data retaining circuit;

a third reset circuit in which a drain terminal and a source terminal of the seventh NMOS are respectively connected to a drain terminal and a source terminal of the third reset circuit in second retaining circuit; and

a fourth reset circuit arranged between the high potential side power supply and an output end of the fourth inverter, i.e., an output signal terminal of the reversed phase of the flip-flop circuit,

wherein the normal phase reset signal is input to a control terminal of each of the second reset circuit and the third reset circuit, and the reversed phase reset signal having a phase opposite to the normal phase reset signal is input to a control terminal of each of the first reset circuit and the fourth reset circuit.

12. The flip-flop circuit according to claim 8, wherein the master side element and the slave side element further comprising reset devices,

wherein the reset devices comprises:

a first reset circuit arranged between the high potential side power supply and the output end of the second inverter, i.e., the output end of the master side element;

a second reset circuit in which a drain terminal and a source terminal of the first NMOS are respectively connected to a drain terminal and a source terminal of the second reset circuit in first data retaining circuit;

a third reset circuit in which a drain terminal and a source terminal of the seventh NMOS are respectively connected to a drain terminal and a source terminal of the third reset circuit in second retaining circuit; and

a fourth reset circuit arranged between the high potential side power supply and an output end of the fourth inverter, i.e., an output signal terminal of the reversed phase of the flip-flop circuit,

wherein the normal phase reset signal is input to a control terminal of each of the second reset circuit and the third reset circuit, and the reversed phase reset signal having a phase opposite to the normal phase reset signal is input to a control terminal of each of the first reset circuit and the fourth reset circuit.

13. The flip-flop circuit according to claim 7, wherein the first data reading circuit and the first data retaining circuit in the master side element and the second data reading circuit and the second data retaining circuit in the slave side element further include power-down devices for inputting a power-down signal for turning off a power supply,

wherein the power-down devices comprises:

a first power-down circuit arranged between the high potential side power supply and a source of each of the first PMOS and the second PMOS of the first data reading circuit in the master side element;

a second power-down circuit arranged between the high potential side power supply and a power supply end of the first inverter and the second inverter of first data retaining circuit in the master side element;

a third power-down circuit arranged between the high potential side power supply and a source of each of the third PMOS and the fourth PMOS of the second data reading circuit in the slave side element; and

a fourth power-down circuit arranged between the high potential side power supply and a power supply end of the third inverter and the fourth inverter of second data retaining circuit in the slave side element,

and wherein the power-down signal for turning off a power supply is configured to input to a control terminal of each of the first power-down circuit, the second power-down circuit, the third power-down circuit, and the fourth power-down circuit.

14. The flip-flop circuit according to claim 8, wherein the first data reading circuit and the first data retaining circuit in the master side element and the second data reading circuit and the second data retaining circuit in the slave side element further include power-down devices for inputting a power-down signal for turning off a power supply,

wherein the power-down devices comprises:

a first power-down circuit arranged between the high potential side power supply and a source of each of the first PMOS and the second PMOS of the first data reading circuit in the master side element;

a second power-down circuit arranged between the high potential side power supply and a power supply end of the first inverter and the second inverter of first data retaining circuit in the master side element;

a third power-down circuit arranged between the high potential side power supply and a source of each of the third PMOS and the fourth PMOS of the second data reading circuit in the slave side element; and

a fourth power-down circuit arranged between the high potential side power supply and a power supply end of the third inverter and the fourth inverter of second data retaining circuit in the slave side element,

and wherein the power-down signal for turning off a power supply is configured to input to a control terminal of each of the first power-down circuit, the second power-down circuit, the third power-down circuit, and the fourth power-down circuit.

18. A frequency dividing circuit comprising a logical circuit and the flip-flop circuit according to claim 1.

19. A frequency dividing circuit comprising a logical circuit and the flip-flop circuit according to claim 2.

20. A frequency dividing circuit comprising a logical circuit and the flip-flop circuit according to claim 3.

21. A frequency dividing circuit comprising a logical circuit and the flip-flop circuit according to claim 4.

22. A frequency dividing circuit comprising a logical circuit and the flip-flop circuit according to claim 5.

23. A frequency dividing circuit comprising a logical circuit and the flip-flop circuit according to claim 6.

24. A frequency dividing circuit comprising a logical circuit and the flip-flop circuit according to claim 7.

25. A frequency dividing circuit comprising a logical circuit and the flip-flop circuit according to claim 8.

26. A frequency dividing circuit comprising a logical circuit and the flip-flop circuit according to claim 9.

27. A frequency dividing circuit comprising a logical circuit and the flip-flop circuit according to claim 10.

28. A frequency dividing circuit comprising a logical circuit and the flip-flop circuit according to claim 11.

29. A frequency dividing circuit comprising a logical circuit and the flip-flop circuit according to claim 12.

30. A frequency dividing circuit comprising a logical circuit and the flip-flop circuit according to claim 13.

31. A frequency dividing circuit comprising a logical circuit and the flip-flop circuit according to claim 14.

15. A flip-flop circuit comprising a master side element including a first data reading circuit and a first data retaining circuit and a slave side element including a second data reading circuit and a second data retaining circuit,

wherein a power supply of the second data reading circuit is controlled by a normal phase clock signal input from an outside, and a power supply of the first data reading circuit is controlled by a reversed phase clock signal having a phase opposite to the normal phase clock signal, wherein the first data reading circuit includes a differential circuit, and wherein the first data retaining circuit, the second data reading circuit, and the second data retaining circuit include inverter circuits.

16. The flip-flop circuit according to claim 15, wherein the second data retaining circuit is configured such that an input end and an output end of a third inverter are interconnected with an output end and an input end of a fourth inverter, wherein an earthing end of the third inverter and the fourth inverter is connected to a low potential side power supply, and wherein a power supply end of the third inverter and the fourth inverter is connected to a high potential side power supply.

17. The flip-flop circuit according to claim 16, wherein the second data reading circuit includes a fifth inverter, a sixth inverter, and a seventh NMOS,

wherein an input end of the third inverter in the second data retaining circuit is connected to an output end of the fifth inverter, and an input end of the fourth inverter in the second data retaining circuit is connected to an output end of the sixth inverter,

and wherein an earthing end of each of the fifth inverter and the sixth inverter is connected to the low potential side power supply via the seventh NMOS, and a power supply end of each of the fifth inverter and the sixth inverter is connected to the high potential side power supply.

32. A frequency dividing circuit comprising a logical circuit and the flip-flop circuit according to claim 15.

33. A frequency dividing circuit comprising a logical circuit and the flip-flop circuit according to claim 16.