INTEGRATED DMOS AND SCHOTTKY

• US 20110156810A1
• Filed: 11/12/2010
• Published: 06/30/2011
• Est. Priority Date: 12/30/2009
• Status: Abandoned Application

• Current Assignee: Intersil Americas LLC (Renesas Electronics Corporation)
• Original Assignee: Intersil Americas LLC (Renesas Electronics Corporation)
• Inventors: Church, Michael David, Girdhar, Dev Alok
• Application Number:
  US12/944,836
• Publication Number:
  US 20110156810A1
• Time in Patent Office: Days
• US Class Current: 327/566
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/782 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Embodiments relate generally to voltage converter structures including a diffused metal oxide semiconductor (DMOS) field effect transistors (FET). Embodiments include the combination of DMOS devices (e.g., FETs with isolated bodies from the substrate) with Schottky diodes on a single semiconductor die. The Schottky diode can be integrated into a cell of a DMOS device by forming an N-type area in the P-body region of the DMOS device.

Claims

1. A semiconductor device voltage converter, comprising:

a semiconductor die having a circuit side and a non-circuit side; and

an output stage on the circuit side of the semiconductor die, the output stage comprising;

a lateral N-type diffusion metal oxide semiconductor (NDMOS) device having a body isolated from the non-circuit side of the semiconductor die; and

a Schottky diode integrated into the semiconductor die;

wherein the Schottky diode is integrated into a cell of the NDMOS device by forming an n-type area in a P-body region of the NDMOS device.

2. The semiconductor device voltage converter of claim 1, wherein in a cross section perpendicular to the circuit side of the semiconductor die, a gate of the NDMOS device and an anode of the Schottky diode are coplanar in a plane which is parallel with the circuit side of the semiconductor die.

3. The semiconductor device voltage converter of claim 1, wherein the Schottky diode comprises:

an anode formed by a source metal of the NDMOS; and

a cathode terminal formed by a drain metal of the NDMOS.

4. The semiconductor device voltage converter of claim 3, wherein the Schottky diode comprises a Schottky metal.

5. The semiconductor device voltage converter of claim 4, wherein the Schottky metal comprises at least one of Ti, Co, Pt, and wherein contact of the metals with silicon form metal silicides comprising TiSi₂, CoSi₂, PtSi₂, and combinations thereof.

6. The semiconductor device voltage converter of claim 1, further comprising:

the output of the output stage comprises a drain of the NDMOS device and a cathode terminal of the Schottky diode.

7. The semiconductor device voltage converter of claim 1, further comprising:

a second lateral NDMOS device wired in parallel with the first lateral NDMOS to configure a single transistor, and wherein the Schottky diode is integrated into a cell of the second NDMOS device by forming an n-type area in a P-body region of the second NDMOS device.

8. The semiconductor device voltage converter of claim 1, wherein the Schottky diode comprises a junction barrier N-type Schottky region.

9. The semiconductor device voltage converter of claim 8, wherein the junction barrier Schottky region has a width selected to optimize on voltage (V_on) characteristics and breakdown voltage characteristics of the voltage converter.

10. The semiconductor device voltage converter of claim 9, wherein the junction barrier Schottky region has about an equal dopant concentration as an N-type diffusion region of the NDMOS device.

11. The semiconductor device voltage converter of claim 1, wherein a current path through the Schottky diode dominates over a current path through a drain/body PN junction.

12. The semiconductor device voltage converter of claim 11, wherein the Schottky diode begins conducting first, thereby limiting the forward bias voltage across the drain/body PN junction, such that less minority carries are generated at the PN junction, thereby obtaining a faster switching speed.

13. A semiconductor device voltage converter, comprising:

a semiconductor die having a circuit side and a non-circuit side; and

an output stage on the circuit side of the semiconductor die, the output stage comprising;

a quasi vertical N-type diffusion metal oxide semiconductor (QVDMOS) device;

a Schottky diode integrated into the semiconductor die; and

an output;

wherein the Schottky diode is integrated into a cell of the QVDMOS device by forming an n-type area in a P-body region of the QVDMOS device.

14. The semiconductor device voltage converter of claim 13, wherein in a cross section perpendicular to the circuit side of the semiconductor die, a gate of the QVDMOS device and an anode of the Schottky diode are coplanar in a plane which is parallel with the circuit side of the semiconductor die.

15. The semiconductor device voltage converter of claim 14, wherein the Schottky diode comprises a Schottky metal.

16. The semiconductor device voltage converter of claim 15, wherein the Schottky metal comprises at least one of at least one of Ti, Co, Pt, and wherein contact of the metals with silicon form metal silicides comprising TiSi₂, CoSi₂, PtSi₂, and combinations thereof.

17. The semiconductor device voltage converter of claim 13, further comprising:

a second QVDMOS device wired in parallel with the first QVDMOS device to configure a single transistor, and wherein the Schottky diode is integrated into a cell of the second QVDMOS device by forming an n-type area in a P-body region of the second QVDMOS device.

18. The semiconductor device voltage converter of claim 13, wherein a drain of the QVDMOS device is isolated from a source, a body, and a gate of the QVDMOS device.

19. The semiconductor device voltage converter of claim 13, wherein the Schottky diode comprises a junction barrier N-type Schottky region.

20. The semiconductor device voltage converter of claim 17, wherein the junction barrier Schottky region has a width selected to optimize on voltage (V_on) characteristics and breakdown voltage characteristics of the voltage converter.

21. The semiconductor device voltage converter of claim 20, wherein the junction barrier Schottky region has about an equal dopant concentration as an N-type diffusion region of the NDMOS device.

22. The semiconductor device voltage converter of claim 13, wherein a current path through the Schottky diode dominates over a current path through a drain/body PN junction.

23. The semiconductor device voltage converter of claim 22, wherein the Schottky diode begins conducting first, thereby limiting the forward bias voltage across the drain/body PN junction, such that less minority carries are generated at the PN junction, thereby obtaining a faster switching speed.

24. A method for forming a semiconductor device voltage converter, comprising:

forming an output stage on a single semiconductor die with a method comprising;

forming a lateral N-type diffusion metal oxide semiconductor (NDMOS) device having a body isolated from a non-circuit side of the semiconductor die;

forming a Schottky diode integrated into the semiconductor die; and

forming an output of the output stage;

electrically connecting the output of the output stage to a non-circuit side of the semiconductor die,

wherein the Schottky diode is integrated into a cell of the NDMOS device by forming an n-type area in a P-body region of the NDMOS device.

25. A method for forming a semiconductor device voltage converter, comprising:

forming an output stage on a single semiconductor die with a method comprising;

forming a quasi vertical N-type diffusion metal oxide semiconductor (QVDMOS) device having a body isolated from a non-circuit side of the semiconductor die;

forming a Schottky diode integrated into the semiconductor die; and

forming an output of the output stage;

electrically connecting the output of the output stage to a non-circuit side of the semiconductor die,

wherein the Schottky diode is integrated into a cell of the QVDMOS device by forming an n-type area in a P-body region of the QVDMOS device.

26. An electronic system comprising:

a voltage converter device, comprising;

a semiconductor die comprising a circuit side and a non-circuit side;

a lateral N-type diffusion metal oxide semiconductor (NDMOS) device having a body isolated from a non-circuit side of the semiconductor die;

a Schottky diode integrated into the semiconductor die, wherein the Schottky diode is integrated into a cell of the NDMOS device by forming an n-type area in a P-body region of the NDMOS device; and

an output stage, wherein the output stage is electrically connected to the to the drain region of the low side NDMOS;

a processor electrically coupled to the voltage converter device through a first data bus;

memory electrically coupled to the processor through a second data bus; and

a power source which powers the voltage converter device, the processor, and the memory.

27. The electronic system of claim 26, wherein the Schottky diode is integrated into the NDMOS at a cell spacing selected from every cell, every other cell, and every 5^th cell.

28. An electronic system comprising:

a voltage converter device, comprising;

a semiconductor die comprising a circuit side and a non-circuit side;

a quasi vertical N-type diffusion metal oxide semiconductor (QVDMOS) device having a body isolated from a non-circuit side of the semiconductor die;

a Schottky diode integrated into the semiconductor die, wherein the Schottky diode is integrated into a cell of the QVDMOS device by forming an n-type area in a P-body region of the QVDMOS device; and

an output stage, wherein the output stage is electrically connected to the to the drain region of the low side QVDMOS;

a processor electrically coupled to the voltage converter device through a first data bus;

memory electrically coupled to the processor through a second data bus; and

a power source which powers the voltage converter device, the processor, and the memory.

29. The electronic system of claim 28, wherein the Schottky diode is integrated into the QVDMOS at a cell spacing selected from every cell, every other cell, and every 5^th cell.